Vendor: Renesas Category: PLL

1.4GHz Analog PLL for Skew Adjust IP

1.4GHz Analog PLL for Skew Adjust IP on TSMC's 28nm HPC+

TSMC 28nm HPC+ Available on request View all specifications

Overview

The AT28_PLL0002SK1P7G18V1B is a 1.4GHz analog phase-locked loop (PLL) IP for skew adjust using TSMC's 28nm HPC+ (High-Performance Compact Plus) process technology.

Parameter Min Max Unit
Operating Voltage (AVDD) 1.62 1.98 V
Operating Voltage (VDD) 0.935 1.08 V
Junction Temperature -40 125 °C
Input Clock — Duty 30 70 %
Input Clock — Rise/Fall time - 0.2 ns

Key features

  • Includes a loop filter
  • VCO operating range: 672MHz to 1400MHz
  • Output frequency range: 48MHz to 1400MHz
  • Input frequency range: 12MHz to 400MHz
  • Multiplying (output frequency/phase frequency detector (PFD) frequency)
    • 14, 28, and 56
  • Divider
    • 4-bit feedback divider, 2-bit input divider, and 4-bit output divider
  • Power-down mode
  • SSC input is not available
  • Power-on sequence is constraint-free
  • Standby (STBY) sequence is constraint-free
  • Process: TSMC 28nm HPC+

Block Diagram

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Silicon Options

Foundry Node Process Maturity
TSMC 28nm HPC+ Available on request

Specifications

Identity

Part Number
AT28_PLL0002SK1P7G18V1B
Vendor
Renesas
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Renesas
HQ: Japan

Learn more about PLL IP core

Frequently asked questions about PLL IP cores

What is 1.4GHz Analog PLL for Skew Adjust IP?

1.4GHz Analog PLL for Skew Adjust IP is a PLL IP core from Renesas listed on Semi IP Hub. It is listed with support for tsmc Available on request.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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