Vendor: Renesas Category: PLL

4.1GHz Analog PLL for Frequency Multiplying IP

4.1GHz Analog PLL for Frequency Multiplying IP on TSMC 16nm FF+

TSMC 16nm FF+GL Available on request View all specifications

Overview

Analog-PLL For Frequency Multiplying on TSMC 16nm FF+

Operating Condition

Parameter Min Max Unit
Operating Voltage  (AVDD) 1.62 1.98 V
Operating Voltage  (VDD) 0.745 0.88 V
Junction Temperature -40 125 °C
Input Clock Duty 27 70 %
Rise/Fall time - 0.2 ns

Key features

  • Includes a loop filter
  • VCO operating range: 2000MHz to 4096MHz
  • Output frequency range: 1000MHz to 2048MHz
  • Input frequency range: 12.5MHz to 200MHz
  • Multiplying (output frequency/phase frequency detector (PFD) frequency): 40 to 120
  • Divider
    • 7-bit feedback divider and 3-bit input divider
  • Power-down mode
  • Multiple outputs with post-divider
  • Power-on sequence is constraint-free
  • Standby (STBY) sequence is constraint-free
  • Process: TSMC 16nm FF+

Block Diagram

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Silicon Options

Foundry Node Process Maturity
TSMC 16nm FF+GL Available on request

Specifications

Identity

Part Number
AT16CPLL0000MP4P1G18V1A
Vendor
Renesas
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Renesas
HQ: Japan

Learn more about PLL IP core

Frequently asked questions about PLL IP cores

What is 4.1GHz Analog PLL for Frequency Multiplying IP?

4.1GHz Analog PLL for Frequency Multiplying IP is a PLL IP core from Renesas listed on Semi IP Hub. It is listed with support for tsmc Available on request.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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