Vendor: Renesas Category: PLL

3GHz SSCG PLL on TSMC 22nm

ADPLL For Spread Spectrum Clock on TSMC T22ULP

TSMC 22nm ULL Available on request View all specifications

Overview

This core is ADPLL(All Digital PLL) with SSCG(Spread Spectrum Clock Generator). This core is not able to adjust the output clock delay using the external delay.

Key features

  • Supply voltage : min=0.81V, typ=0.9V, max=1.05V
  • Operating temperature (Tj) : -40 - +125°C
  • DCO frequency range : 900MHz - 3000MHz
  • Output frequency range : 56.25MHz - 3000MHz
  • Input frequency range : 8MHz - 192MHz
  • Multiplying
    • Output frequency / Input frequency :  0.293 - 375
  • Fractional multiplying available
  • SSC Modulation frequency : 3kHz - 30kHz(target) (Dithered frequency mode)
  • SSC modulation depth :
    • 0.25% - 3.0% down spread (Dithered frequency mode)
    • +/-0.125% - +/-1.5% center spread (Dithered frequency mode)
  • Divider
  • 21bit feedback divider (N divider)
  • 4bit input divider ( M divider )
  • 3bit output divider ( P divider )
  • No external device is needed.

Block Diagram

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Silicon Options

Foundry Node Process Maturity
TSMC 22nm ULL Available on request

Specifications

Identity

Part Number
3GHz SSCG PLL
Vendor
Renesas
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Renesas
HQ: Japan

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is 3GHz SSCG PLL on TSMC 22nm?

3GHz SSCG PLL on TSMC 22nm is a PLL IP core from Renesas listed on Semi IP Hub. It is listed with support for tsmc Available on request.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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