Vendor: True Circuits, Inc. Category: PLL

TSMC CL013G 130nm Deskew PLL - 136MHz-680MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.

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TSMC 130nm G View all specifications

Overview

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the clock reference by an integer between 1 and 4. It provides three 50% duty cycle skew aligned outputs that are divided down from the internal VCO frequency by 1, 2, and 4.

Key features

  • Designed to eliminate clock distribution latency in systems and individual chips.
  • Precisely aligns the clock distribution output with a reference clock.
  • Provides a zero-delay feedback divider and zero-skew divided clock outputs.

What’s Included?

  • GDSII (100% DRC and LVS clean)
  • LVS Spice netlist
  • Verilog model
  • Synopsys synthesis model
  • LEF for clock generator PLL
  • User Guidelines including:
    • integration guidelines,
    • layout guidelines,
    • testability guidelines,
    • packaging guidelines,
    • board-level guidelines

Silicon Options

Foundry Node Process Maturity
TSMC 130nm G —

Specifications

Identity

Part Number
TCI-T13G-DSMPLL
Vendor
True Circuits, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact True Circuits, Inc.

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Frequently asked questions about PLL IP cores

What is TSMC CL013G 130nm Deskew PLL - 136MHz-680MHz?

TSMC CL013G 130nm Deskew PLL - 136MHz-680MHz is a PLL IP core from True Circuits, Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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