What is 1.25GHz Multiplying PLL on TSMC 40nm?
1.25GHz Multiplying PLL on TSMC 40nm is a PLL IP core from Renesas listed on Semi IP Hub. It is listed with support for tsmc Available on request.
Vendor:
Renesas
Category:
PLL
1.25GHz Multiplying PLL on TSMC 40nm
Analog-PLL For Frequency Multiplying on TSMC 40nm
Overview
Analog-PLL For Frequency Multiplying on TSMC 40LP
Key features
- Including Loop-filter
- VCO operating range : 580 -1250 MHz
- Output frequency range : 72.5 –1250 MHz
- Input frequency range : 9.6 -100MHz
- Multiplying (Output freq. / PFD freq.) : 40 -120
- Divider -7bit feedback divider (N divider) -3bit input divider ( M divider )
- Selectable feedback loop for skew adjust
- Power-down Mode is supported
- Multiple outputs with post-divider
- SSC Input is available (recommend triangle profile)
- Power-on sequence is constraint-free
- STBY sequence is constraint-free
Block Diagram
Click to open fullscreen
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 40nm | LP | Available on request |
Specifications
Identity
Part Number
1.25GHz Multiplying PLL
Vendor
Renesas
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Japan
Frequently asked questions about PLL IP cores
How should engineers evaluate this PLL?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.