Vendor: Renesas Category: PLL

4GHz Analog PLL for Frequency Multiplying IP

Analog-PLL For Frequency Multiplying on TSMC 28nm HPC+

TSMC 28nm HPC+ Available on request View all specifications

Overview

The AT28_PLL0000MPFR4G18V1B is a 4GHz analog phase-locked loop (PLL) IP for frequency multiplying using TSMC's 28nm HPC+ (High-Performance Compact Plus) process technology.

Operating Condition

Parameter Min Max Unit
Operating Voltage (AVDD) 1.62 1.98 V
Operating Voltage (VDD) 0.935 1.08 V
Junction Temperature -40 125 °C
Input Clock — Duty 30 70 %
Input Clock — Rise/Fall time - 0.2 ns

Key features

  • Includes a loop filter
  • VCO operating range: 2000MHz to 4000MHz
  • Output frequency range: 62.5MHz to 4000MHz
  • Input frequency range: 20MHz to 200MHz
  • Multiplying (output frequency/phase frequency detector (PFD) frequency)
    • 1.5625 to 200
  • Divider
    • 7-bit feedback divider, 3-bit input divider, and 3-bit output divider
  • 14-bit fractional accuracy
  • Power-down mode
  • SSC input is available (recommend triangle profile)
  • VCO operating range: 2000MHz to 4096MHz
  • Process: TSMC 28nm HPC+

Block Diagram

Silicon Options

Foundry Node Process Maturity
TSMC 28nm HPC+ Available on request

Specifications

Identity

Part Number
AT28_PLL0000MPFR4G18V1B
Vendor
Renesas
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Japan

Learn more about PLL IP core

Frequently asked questions about PLL IP cores

What is 4GHz Analog PLL for Frequency Multiplying IP?

4GHz Analog PLL for Frequency Multiplying IP is a PLL IP core from Renesas listed on Semi IP Hub. It is listed with support for tsmc Available on request.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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