ONFI 4.2 NAND Flash Controller & PHY IP Compliant to JEDEC
The NAND Flash landscape is changing and the NAND Flash Controller IP Core is changing in accordance with it.
- Controller + PHY
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
ONFI 4.2 NAND Flash Controller & PHY IP Compliant to JEDEC
The NAND Flash landscape is changing and the NAND Flash Controller IP Core is changing in accordance with it.
Classical CAN, also known as CAN 2.0 Bus Controller IP, is the foundational CAN bus standard.
The xSPI PHY is designed to work with both the xSPI/PSRAM and the xSPI master host controller IPs.
Flow's Parallel Processing Unit solves one of computing's most fundamental dilemmas - parallel processing.
The CSENT-TX core implements a transmitter for the Single Edge Nibble Transmission (SENT) protocol.
The CSENT-RX core implements a receiver for the Single Edge Nibble Transmission (SENT) protocol.
The MIPI® D-PHY RX+ is a proprietary implementation of the MIPI Camera Serial Interface 2 (CSI-2) and Display Serial Interface (D…
The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.
The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology.
MIPI D-PHY/LVDS Combo Transmitter IP
The MXL-LVDS-DPHY-DSI-TX is a combo PHY that consists of a high-frequency low-power, low-cost, source-synchronous, Physical Layer…
HDCP Authentication Software Stack
The High-bandwidth Digital Content Protection (HDCP) Authentication Software Stack implements HDCP capability in a Trilinear Disp…
The DisplayPort Link Policy Maker (LPM) is a DisplayPort 1.4/2.0 compliant software stack that manages and controls the DisplayPo…
Unified Architecture for Cutting-Edge Intelligence
Multi-channel DVB-C / J83 FEC encoder
The CMS0044 J.83abc/DVB-C Cable FEC Encoder combines all of the channel coding and Forward Error Correction functions specified b…
The CMS0045 ISDB-T Modulator provides all the necessary processing steps to modulate one, two or three transport stream into a co…
The CMS0077 Satellite FEC Decoder has been designed specifically to meet the requirements of the DVB-S2 and DVB-S2X wide-band dig…
The I²C slave core is a simple I²C slave that provides a link between the I²C bus and the AMBA APB.
The Universal Serial Bus Debug Communication Link (USBDCL) provides an interface between an USB 2.0 bus and an AMBA-AHB bus.
Configurable RISC-V processor IP core
The NOEL3 is a configurable RISC-V processor IP core, described in VHDL.
Built on the success of Helion's industry proven cryptographic IP cores, the Helion ESP Engine provides hardware acceleration of …