Ethernet Switch/Router Enterprise 9x10G + 2x25G
This is a L2 switch and an IP/MPLS router with ACL engines.
- Ethernet
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Ethernet Switch/Router Enterprise 9x10G + 2x25G
This is a L2 switch and an IP/MPLS router with ACL engines.
Ethernet Switch/Router Datacenter ToR 32x100G
This L2/L3 Ethernet Switching/Routing Core offers full wire-speed on all 32 ports, with up to 100 Gbit of bandwidth per port.
Ethernet Switch/Router IPSec/MACSec 9x10G + 2x40G
This L2/L3 Ethernet Switching/Routing Core offers full wire-speed on all 11 ports.
The USB device core is compliant with revision 1.1.
Safety Enhanced GPNPU Processor IP
Automotive applications are uniquely demanding for any AI acceleration solution.
The Network on Chip (NOC) technology redefines typical NOC capabilities as it extends the on-chip network beyond chip(let) bounda…
USB Full Speed Transceiver
UCIe Controller add-on CXL2 Protocol Layer
The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…
UCIe Controller add-on CXL3 Protocol Layer
The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…
UCIe Controller baseline for Streaming Protocols for ASIL B Compliant, AEC-Q100 Grade 2
The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…
Bluetooth Low Energy 6.0 Scalable RF IP
The SB1001 Scalable RF Transceiver IP is designed to maximise Performance per μW across the full range of BLE applications, enabl…
Controller + ATC + ATS + DTI · CXL.io · CXL.cache · CXL.mem · Memory pooling
ARC Functional Safety Software
Today’s complex automotive applications require robust safety related hardware and software to meet the increasingly stringent au…
The NVMe Verification IP (VIP) and Post-Silicon Validation Suite are based on the latest protocol standards (NVMe 1.2) from www.n…
AI DSA Processor - 9-Stage Pipeline, Dual-issue
NI900 is a DSA processor based on 900 Series.
ARC-V RPX Series Functional Safety Processor IP
The ARC-V™ RPX-110 series functional safety (FS) processors, which include the RPX-110-FS, RPX-115-FS, RPX-110V-FS, and RPX-115V-…
Double & Single Precision IEEE-754 complete FPU
The A2FD is a fully synthesizable module implemented in Verilog RTL.
Very high performance IEEE-754 modules
The A2FM product is a collection of floating-point execution units compliant with the ANSI/IEEE Std 754-1985, IEEE Standard for B…
Traditional processors no longer strike the right balance between high performance, energy consumption, and cost.
Automated Hierarchical Test for Analog/Mixed Signal IPs The SLM SHS IP is an automated hierarchical test solution for efficiently…