Serial Lite II Intel® FPGA IP Core
Altera
•
HQ:
USA
The Serial Lite II Intel® FPGA IP core provides a simple and lightweight way to move data from one point to another reliably at h…
- Ethernet
Compare 1,022 High-Speed Serial IP Cores from 131 vendors
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Altera• HQ: USA
The serial digital interface (SDI) II Intel FPGA intellectual property (IP) core implements a transmitter, receiver or full-duple…
- Video Transport
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Altera• HQ: USA
Intel is discontinuing the intellectual property (IP) for RapidIO I and RapidIO II Intel offers two distinct Intel® FPGA IPs for …
- RapidIO
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Scalable Switch Intel® FPGA IP for PCI Express
Altera• HQ: USAThe Scalable Switch Intel® FPGA IP for PCI Express is a fully configurable switch that implements one fully configurable upstream…
- PCI Express
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Altera• HQ: USA
Agilex™ 5 FPGAs and SoC FPGAs are monolithic designs with integrated high-speed transceivers (GTS) and hardened PCIe controller I…
- PCI Express
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Altera• HQ: USA
The F-Tile Intel® Hard IP supports PCIe* configurations up to 4.0 x16 in Endpoint (EP), Root Port (RP), and Transaction Layer (TL…
- PCI Express
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Intel® Arria® 10 and Intel® Cyclone® 10 PCIe Hard IP
Altera• HQ: USAIntel® Arria® 10 and Intel® Cyclone® 10 GX FPGAs include a configurable, hardened protocol stack for PCI Express* that is complia…
- PCI Express
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Multichannel DMA Intel FPGA IP for PCI Express*
Altera• HQ: USAThe Multichannel DMA IP for PCI Express provides high efficiency, speed, and configuration flexibility to support various applica…
- PCI Express
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Low Latency Ethernet 10G MAC FPGA IP
Altera• HQ: USAThe Low Latency Ethernet 10G MAC FPGA IP core (soft IP) offers low round-trip latency, and an efficient resource footprint.
- Ethernet
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Altera• HQ: USA
The JEDEC committee created the JESD204 data converter serial interface standard to standardize and reduce the number of data inp…
- JESD204
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Altera• HQ: USA
The Interlaken Intel® FPGA IP core is Interlaken Protocol Definition v1.2 compliant and allows system developers to achieve high …
- Interlaken
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Interlaken Look-Aside Intel® FPGA IP
Altera• HQ: USAInterlaken Look-Aside is a scalable protocol that allows interoperability between a datapath device and a look-aside coprocessor …
- Interlaken
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Altera• HQ: USA
The enhanced Common Public Radio Interface (eCPRI) Altera® FPGA IP core implements the eCPRI specification version 2.0.
- CPRI
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Compute Express Link (CXL) FPGA IP
Altera• HQ: USAIndustry's first FPGA-based hardened CXL IP solution for Type 1, 2, and 3 devices.
- CXL
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Altera• HQ: USA
The Common Public Radio Interface (CPRI) Altera® FPGA IP core implements the CPRI Specification V7.0.
- CPRI
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Intel® Agilex™ 7 F-Tile Ethernet Hard IP
Altera• HQ: USAThe Intel® Agilex™ 7 FPGA F-Tile incorporates a fracturable, configurable, hardened Ethernet protocol stack for supporting rates …
- Ethernet
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Altera• HQ: USA
The 50G Ethernet Intel® FPGA IP core implements the 25G & 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Cons…
- Ethernet
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Altera• HQ: USA
This IP core implements the 25G and 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium.
- Ethernet
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Intellectual Highway, Corp.• HQ: Japan
Filtering with packet payload scanning Message filters are placed in the middle of a TCP / TLS session to scan application data, …
- Ethernet
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Intellectual Highway, Corp.• HQ: Japan
Full hardware TCP/UDP protocol stack realize both high performance and guaranteed delivery Our TCP/UDP offload engine supports si…
- Ethernet