32-bit RISC-V core with in-order single issue pipeline for Linux-based systems
32-bit RISC-V core with in-order pipeline.
- RISC-V
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
32-bit RISC-V core with in-order single issue pipeline for Linux-based systems
32-bit RISC-V core with in-order pipeline.
64-bit Multiprocessor with Level-2 Cache-Coherence
AndesCore™ AX25MP 64-bit multicore CPU IP is based on AndeStar™ V5 architecture.
Fast Fourier Transformation (FFT) calculation IP block.
Third-Generation, High-Performance CPU Based on DynamIQ Technology Built for powering next-generation 5G solutions Designed for d…
Library of mathematical and floating point (FP) components
Optimized for efficient hardware implementation, the Synopsys Foundation Cores include a library of mathematical and floating poi…
As more functionality is integrated into an SoC, it is costly and time consuming to develop and maintain necessary functional blo…
Machine vision and deep learning are being embedded in integrated SoCs and expanding into high-volume applications such as automo…
Synopsys offers a suite of development tools, ARC development systems and operating systems, providing everything a developer nee…
Synopsys has a long history of working with DSP customers to meet the ever-increasing computation requirements, offering lowest p…
The Synopsys ARC® EM Family, based on the ARCv2 instruction set architecture (ISA) includes ARC EM4 and EM6, DSP-enhanced EMxD pr…
The latest additions to the Synopsys ARC® ARC HS family, the 32-bit ARC HS5x and 64-bit HS6x processors, are based on the new ARC…
DVB-S2X-LDPC Decoder
LDPC codec for NAND FLASH error correction
The LDPC IP is aLow-densityparity-check code encoder and decoder designed for 3D NAND Flash error correction to address the relia…
PowerVR Neural Network Accelerator
The Series3NX-F brings programmable extensibility to the Series3NX architecture.
AI and DSP performance leader with up to 4X the NN performance and 2X the DSP performance of the HiFi 4 DSP, ideal for digital as…
First High Performance Split-Lock DynamIQ CPU
The all new Arm Cortex-A family of Automotive Enhanced (AE) high performance processors is designed for devices undertaking compl…
The IPrium-ATSC-8VSB-Modulator IP Core implements the USA DTV standard ATSC A/53 Part 2.
TC5300 is an efficient Polar encoder/decoder Core solution compliant with 3GPP NR (5G) specifications.
TC5200 is an efficient LDPC encoder/decoder Core solution fully compliant with 3GPP NR (5G) specifications.
ASIC IP-core for very-high-throughput decoding (>20G) of 3GPP 5G Release 15
Very high throughput (>20 Gbps) LDPC decoder and encoder for 3GPP 5G Release 15.