The ARC® HS66 and HS68 processors feature a dual-issue, 64-bit superscalar architecture for use in embedded applications where hi…
- ARC
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
The ARC® HS66 and HS68 processors feature a dual-issue, 64-bit superscalar architecture for use in embedded applications where hi…
ARC HS66 64-bit, dual-issue processor core, interconnect, ARCv3 ISA, for embedded applications
The ARC® HS66 and HS68 processors feature a dual-issue, 64-bit superscalar architecture for use in embedded applications where hi…
The ARC® HS56, HS57D and HS58 processors feature a dual-issue, 32-bit superscalar architecture for use in embedded applications w…
The ARC® HS56, HS57D and HS58 processors feature a dual-issue, 32-bit superscalar architecture for use in embedded applications w…
ARC HS57DMP multi-core version of dual-issue HS57D ARCv3DSP ISA, with I&D cache
The ARC® HS56, HS57D and HS58 processors feature a dual-issue, 32-bit superscalar architecture for use in embedded applications w…
ARC HS57D 32-bit, dual-issue processor core and interconnect, ARCv3DSP ISA, with I&D cache
The ARC® HS56, HS57D and HS58 processors feature a dual-issue, 32-bit superscalar architecture for use in embedded applications w…
The ARC® HS56, HS57D and HS58 processors feature a dual-issue, 32-bit superscalar architecture for use in embedded applications w…
ARC HS56 32-bit, dual-issue processor core & interconnect, ARCv3 ISA, for embedded applications
The ARC® HS56, HS57D and HS58 processors feature a dual-issue, 32-bit superscalar architecture for use in embedded applications w…
The ARC® HS46FS, HS46FSx4, HS47DFS, HS47DFSx4, HS48FS, and HS48FSx4 functional safety processors (ARC HS4xFS) simplify developmen…
The ARC® HS46FS, HS46FSx4, HS47DFS, HS47DFSx4, HS48FS, and HS48FSx4 functional safety processors (ARC HS4xFS) simplify developmen…
The ARC® HS46FS, HS46FSx4, HS47DFS, HS47DFSx4, HS48FS, and HS48FSx4 functional safety processors (ARC HS4xFS) simplify developmen…
The ARC® HS46FS, HS46FSx4, HS47DFS, HS47DFSx4, HS48FS, and HS48FSx4 functional safety processors (ARC HS4xFS) simplify developmen…
The ARC® HS46FS, HS46FSx4, HS47DFS, HS47DFSx4, HS48FS, and HS48FSx4 functional safety processors (ARC HS4xFS) simplify developmen…
ARC HS46FS with ASIL B / ASIL D support, including lock-step for functional safety applications
The ARC® HS46FS, HS46FSx4, HS47DFS, HS47DFSx4, HS48FS, and HS48FSx4 functional safety processors (ARC HS4xFS) simplify developmen…
The DSP-enhanced ARC® EMxD and HS4xD Families of embedded 32-bit processors are based on the scalable ARCv2DSP Instruction Set Ar…
The DSP-enhanced ARC® EMxD and HS4xD Families of embedded 32-bit processors are based on the scalable ARCv2DSP Instruction Set Ar…
ARC HS47D 32-bit, dual-issue processor core, ARCv2DSP ISA, with 100+ DSP instructions and I&D cache
The DSP-enhanced ARC® EMxD and HS4xD Families of embedded 32-bit processors are based on the scalable ARCv2DSP Instruction Set Ar…
The ARC® HS45D and HS47D processors feature a dual-issue, 32-bit, RISC + DSP architecture for use in embedded applications where …
ARC HS45Dx2 dual-core version of dual-issue HS45D with ARCv2DSP ISA, with 100+ DSP instructions
The ARC® HS45D and HS47D processors feature a dual-issue, 32-bit, RISC + DSP architecture for use in embedded applications where …
The ARC® HS45D and HS47D processors feature a dual-issue, 32-bit, RISC + DSP architecture for use in embedded applications where …