An interpolating filter chain, numerically controlled oscillator, and mixer comprise the DUC.
- Filters Transforms
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
An interpolating filter chain, numerically controlled oscillator, and mixer comprise the DUC.
Ultra-Low-Power Deeply Embedded RISC-V Processor
The BA51 is a configurable, low-power, deeply embedded RISC-V processor IP core.
Compact LossLess Decoder RTL Core
Extremely high throughput contributes to realization of the complete lossless compression and decompression.
1:6 Fixed Length Visually Lossless Compression/Decompression [RGB/YCbCr]
Fixed Length Visually Lossless Compression [RGB/YCbCr]
1:3 Fixed Length Visually Lossless Compression/Decompression [RGB/YCbCr]
Fixed Length Visually Lossless Compression [RGB/YCbCr]
1:6 Fixed Length Visually Lossless Compression/Decompression [RGB/YCbCr]
Fixed Length Visually Lossless Compression [RGB/YCbCr]
1:4 Fixed Length Visually Lossless Compression/Decompression [RGB/YCbCr]
Fixed Length Visually Lossless Compression [RGB/YCbCr]
1:3 Fixed Length Visually Lossless Compression/Decompression [RGB/YCbCr]
Fixed Length Visually Lossless Compression [RGB/YCbCr]
1:3 Fixed Length Visually Lossless Compression/Decompression [RGB/YCbCr]
Fixed Length Visually Lossless Compression [RGB/YCbCr]
1:2 Fixed Length Visually Lossless Compression/Decompression [RGB/YCbCr]
Fixed Length Visually Lossless Compression [RGB/YCbCr]
H8SX is a high speed 32-bit CPU. It is upward-compatible with H8/300, H8/300H and H8S CPUs on an object level.
H8S CPU subsystem (H8S C200) IP
H8S is a high speed 16-bit CPU with an internal 32-bit architecture, which is upward-compatible with H8/300 and H8/300H CPUs on a…
H8/300 CPU IP ( 8-bit CPU IP )
H8/300 is a high speed 8-bit CPU with an internal 16-bit architecture.
Polar Encoder / Decoder for 5G NR control channels
AccelerComm's Polar IP delivers the 3GPP-compliant encoding and decoding chain for 5G NR control channels.
LDPC Encoder / Decoder for 5G and 6G NTN PHY
High-performance Forward Error Correction IP for 5G and 6G NTN PHY.
32-bit Embedded RISC-V Functional Safety Processor
The EMSA5-FS is a processor core designed for functional safety.
NPU IP for AI Vision and AI Voice
The VIP9000 family offers programmable, scalable and extendable solutions for markets that demand real time and low power AI devi…
LTE Release-10 Baseband PHY. (L1) IP
This is a 3GPP Release 10 compliant LTE eNodeB PHY IP, which is a Macro cell LTE available for commercial deployment of LTE Netwo…
Narrow band - IoT Release-14 e-NodeB PHY. (L1) IP
This LTE UE Reference design is a Category NB UE.
Secure and Scalable Performance for Next-Generation On-The-Go Devices Arm Cortex-A78C is a CPU built on the foundation of Cortex-…