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Vendor:
Synopsys, Inc.
Category:
CPU
Optimized for GHz+ operating speeds with minimum area and power consumption, ARC HS Processors are ideal for very high-performance embedded applications
The latest additions to the Synopsys ARC® ARC HS family, the 32-bit ARC HS5x and 64-bit HS6x processors, are based on the new ARC…
Overview
The latest additions to the Synopsys ARC® ARC HS family, the 32-bit ARC HS5x and 64-bit HS6x processors, are based on the new ARCv3 instruction set architecture (ISA). The previous generation HS processors, based on the efficient ARCv2 instruction set architecture (ISA), include the HS3x, HS4x, and DSP-enhanced HS4xD processors. All HS processors support closely coupled memories (CCMs), which enable single-cycles access to instructions and data.
HS processors are optimized for GHz+ operating speeds with minimum area and power consumption, making them ideally suited for embedded applications with very high-performance requirements. The HS processors are available in single-core, dual-core and quad-core configurations.
The ARC HS processors are supported by a broad ecosystem of commercial and open-source tools, operating systems, and middleware. This includes offerings from leading industry vendors who are members of the ARC Access Program as well as a comprehensive suite of free and open source software available through the embARC.org website
HS processors are optimized for GHz+ operating speeds with minimum area and power consumption, making them ideally suited for embedded applications with very high-performance requirements. The HS processors are available in single-core, dual-core and quad-core configurations.
The ARC HS processors are supported by a broad ecosystem of commercial and open-source tools, operating systems, and middleware. This includes offerings from leading industry vendors who are members of the ARC Access Program as well as a comprehensive suite of free and open source software available through the embARC.org website
Key features
- ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.
- ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.
- Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.
Benefits
- ARC processors are highly configurable, allowing designers to optimize the performance, power and area of each processor instance on their SoC by implementing only the hardware needed.
- The ARChitect wizard enables drag-and-drop configuration of the core, including options for Instruction, program counter and loop counter widths
- Register file sizeTimers, reset and interrupts Byte ordering Memory type, size, partitioning, base address Power management, clock gating Ports and bus protocol Multipliers, dividers and other hardware features Licensable components such as a Memory Protection Unit (MPU), Floating Point Unit (FPU) and Real-Time Trace (RTT).
- Adding/removing instructions
Specifications
Identity
Part Number
dwc_arc_hs_family
Vendor
Synopsys, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about CPU IP cores
What is Optimized for GHz+ operating speeds with minimum area and power consumption, ARC HS Processors are ideal for very high-performance embedded applications?
Optimized for GHz+ operating speeds with minimum area and power consumption, ARC HS Processors are ideal for very high-performance embedded applications is a CPU IP core from Synopsys, Inc. listed on Semi IP Hub.
How should engineers evaluate this CPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.