Hitting the Memory Wall:Why Cache Miss Tolerance Defines CPU Performance Now
This article shares our experience using Google’s FlatBuffers library as a memory subsystem stress test on the Andes AX46MPV RISC-V core.
Vendor:
CloudBEAR, LLC
Category:
CPU
32-bit RISC-V core with in-order single issue pipeline for Linux-based systems
32-bit RISC-V core with in-order pipeline.
Overview
32-bit RISC-V core with in-order pipeline. Tiny Linux-capable processor optimized for low power and small area. Ideally fits IoT applications requiring Linux.
Key features
- Architecture: RV32IMACF
- 32-bit RISC-V with 32 integer registers (I extension)
- Integer multiplication and division (M extension)
- Atomic operation support (A extension)
- Compressed mode for better code density (C extension)
- IEEE 754-2008 compliant single precision floating point (F extension)
- IEEE 754-2008 compliant double precision floating point (D extension)
- Bit manipulation instructions support (B extension)
- Scalar cryptography instructions support (K extension)
- Digital signal processing instructions support (P extension)
- Single instruction issue
- Up to 4 cores in complex
- Machine, Supervisor and User modes
- 8 stage in-order pipeline
- Advanced branch predictor: BTB, BHT, RAS
- Sv32 Virtual Memory support
- 4 to 32 KiB, 2 to 8-way L1 I-cache
- 4 to 32 KiB, 2 to 8-way L1 D-cache
- Integrated 128 KiB to 2 MiB L2 Cache
- L2 stride prefetcher
- Interrupts
- Platform Level Interrupt Controller (PLIC)
- Multi-Core Local Interruptor (CLINT): timer + software interrupts
- Local interrupt support to provide fast handling
- Core Local Interrupt Controller (CLIC)
- Non-Maskable Interrupts (NMIs)
- ECC memory protection (SEC-DED)
- Physical memory protection
- Integrated debug controller including HW breakpoints
- System bus access
- Compact JTAG support
- Power management support
- AXI system interface
- AXI peripheral interface
- AXI front-port interface for peripheral coherent access
- Performance
- 1.72 DMIPS/MHz
- 3.34 CoreMark/MHz
- Frequency
- 1 GHz (TSMC, 40nm G, SSG corner)
- 1.2 GHz (TSMC, 28nm HPC+, SSG corner)
Benefits
- SMP support and accelerator coherency
- BI-350 has up to 4 cores, each with an L1 caches and a single shared L2 cache implementing fully coherent memory system. Additional coherency controller provides coherent access for accelerators via AXI front port to cached memory ranges simplifies software development and improves performance.
- Development Tools
- Complete set of RISC-V tools for fast and convenient software development. Compatible with upstream standard development and debug tools: OpenOCD, GCC, GDB, Eclipse. CloudBEAR also provides pre-configured Eclipse-based IDE with prebuilt toolchain and example projects for easy development start.
- 3rd Party Development Tools
- IAR Embedded Workbench®
- SEGGER Embedded Studio for RISC-V
- TRACE32® debugger for RISC-V.
- Compatible Debug Probes
- BI-350 has integrated Debug module (compliant with RISC-V specification) that allows to use most of standard debug probes. The following debug probes are verified:
- Digilent HS2
- Digilent HS3
- Olimex ARM-USB-TINY
- Olimex ARM-USB-TINY-H
- Olimex ARM-USB-OCD
- Olimex ARM-USB-OCD-H
- IAR I-jet
- SEGGER J-Link
- TRACE32® debugger for RISC-V
Specifications
Identity
Part Number
BI-350
Vendor
CloudBEAR, LLC
Type
Silicon IP
Compute
CPU Architecture
RISC-V
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Russia
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Frequently asked questions about CPU IP cores
What is 32-bit RISC-V core with in-order single issue pipeline for Linux-based systems?
32-bit RISC-V core with in-order single issue pipeline for Linux-based systems is a CPU IP core from CloudBEAR, LLC listed on Semi IP Hub.
How should engineers evaluate this CPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.