ARC-V RHX Series Functional Safety Processor IP
The ARC-V™ RHX-110-FS, RHX-115-FS, RHX-110V-FS, and RHX-115V-FS functional safety processors simplify development of high-perform…
- RISC-V
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
ARC-V RHX Series Functional Safety Processor IP
The ARC-V™ RHX-110-FS, RHX-115-FS, RHX-110V-FS, and RHX-115V-FS functional safety processors simplify development of high-perform…
The ARC-V™ RHX-100 series processors feature a dual-issue, 32-bit superscalar architecture for use in applications where real-tim…
ARC Data Fusion Voice/Speech Option
IoT applications increasingly require sensing capabilities that extend beyond what traditional sensors provide.
NPU IP for Data Center and Automotive
The VIP9400 processing family offers programmable, scalable and extendable solutions for markets that demand real time and AI dev…
Out-of-Order, superscalar, 8-wide decode processor based on the RISC-V RVA23 profile, co-designed and optimized with Tenstorrent Tensix IP
BCH Encoder and Decoder IP Core
The IP Core implements BCH Code encoding and decoding.
The GenAI IP is the smallest version of our NPU, tailored to small devices such as FPGAs and Adaptive SoCs, where the maximum Fre…
32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification
The L31AS is a 32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification.
Neoverse Compute Subsystems N2 (CSS N2)
Neoverse CSS N2: The Arm Neoverse N2 Platform, Delivered to Partners as a Verified, Performance-Validated Customizable Subsystem …
A CPU Foundation for the AI-Driven Datacenter The Arm Neoverse V3 CPU is built to deliver maximum performance for cloud applicati…
Optimal Performance and Power Efficiency for Hyperscale, Telecom, Networking, and Infrastructure Edge Devices The Arm Neoverse N3…
Tensix Cores for specialized acceleration
Tensix NEO® is Tenstorrent’s latest high performance AI architecture, optimized for performance-per-mm2 and performance-per-watt.
AI processing engine - Voice control, Context detection and Sensor applications
AON1020™ belongs to the optimized AONSens™ Neural Network cores for Voice and Audio recognition as well as other sensor applicati…
AI processing engine - Voice control, Context detection and Speaker ID
AON1010™ belongs to the optimized AONVoice™ Neural Network cores for Voice and Audio recognition.
32-bit RISC-V microcontroller.
64-bit RISC-V embedded core with in-order single issue pipeline
64-bit RISC-V embedded core with in-order single issue pipeline.
32-bit RISC-V embedded core with in-order single issue pipeline
32-bit RISC-V embedded core with in-order single issue pipeline.
optimized for generative AI applications running Transformer based NN models that enables efficient and simple system designs.
4x improvement to vector computation with 4x sustained bandwidth of prior generations
Building on the popular SiFive Intelligence™ X280 products’ success in AI/ML applications across mobile, infrastructure and autom…
The highest performance RISC-V core is ideal for consumer applications or used in conjunction with a vector processor in the data…