Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
Pipelined Multiplier with generic width and depth
PIPE_MULT is a general purpose multiplier with a configurable data width and configurable number of pipeline stages.
SIN_X calculates the sine of an angle.
COS_X calculates the cosine of an angle in radians.
SCR5 is an efficient, silicon-proven, entry-level Linux-capable 32/64-bit RISC-V processor core.
SCR4 is a 32/64-bit RISC-V low-power, high-performance, area-optimized processor core with floating-point arithmetic functionalit…
SCR3 is an efficient, silicon-proven, microcontroller-class, 32/64-bit RISC-V processor core.
SCR1 is an open-source and silicon-proven RISC-V-compatible, 32-bit, entry-level, MCU-class core.
High performance, low power, 8-bit processor
The M8051EW and M8051W microcontroller cores are high performance versions of the popular 8051 8-bit microcontroller.
ColdFire V2 Core with AMBA peripherals connected in a subsytem
Building upon the 68K foundation, ColdFire offers RISC performance with industry- code density and a rich set of connectivity per…
64-bit RISC-V core with out-of-order pipeline based complex for Linux-based embedded systems
64-bit RISC-V core with out-of-order pipeline based complex.
32-bit Multiprocessor with Level-2 Cache-Coherence
AndesCore™ A25MP 32-bit multicore CPU IP is based on AndeStar™ V5 architecture.
Single 512-bit SIMD DSP for Vision/Radar/Lidar/AI
Built on our latest Xtensa NX architecture and offers up to 2.18TOPS of performance The Cadence® Tensilica® Vision Q7 DSP deliver…
The 18-bit Pipeline DSP slice IP Core provides the best utilization of device resources like memory, I/O, processor and clock.
Ultra Compact 32-bit RISC-V CPU Core
AndesCore™ N22 is a 32-bit 2-stage pipeline CPU IP core based on AndeStar™ V5 architecture for embedded applications that require…
16 state DVB-RCS2 Turbo Encoder
This is a 16 state DVB-RCS2 compatible parallel concatenated turbo encoder.
Smallest and lowest power DSP for narrowband wireless communications and always-on applications The Cadence® Tensilica® Fusion F1…
Compact High-Speed 64-bit CPU Core
AndesCore™ NX25F is a compact 64-bit CPU IP core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it is t…
FlexCFR is a communications standard agnostic, crest factor reduction solution.
High-performance 32-bit Superscalar Processor
C810 utilizes a 10-stage superscalar pipeline, with a standard memory management unit, and can run Linux and other operating syst…
Energy-efficient 32-bit superscalar processor
C807 utilizes an 8-stage pipeline and dual-issue superscalar architecture, with a standard memory management unit, and can run Li…