6809 compatible 8-bit microprocessor
iniCPU, a 8-bit micro processor, enables embedded computing and controlling on chip.
- CPU
- Silicon proven in ASIC and FPGA Technologies
- now
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
6809 compatible 8-bit microprocessor
iniCPU, a 8-bit micro processor, enables embedded computing and controlling on chip.
Industry reference DVB-RCS turbo decoder
TC1000 implements the turbo code specified by DVB-RCS for Interactive 2-way satellite systems.
The W65C02S IP is a 8-bit 65xx Microprocessor available in GDSII Hardcore, RTL Softcore, and FPGA Specific Firm Cores.
The W65C02S IP is a 8/16-bit 65xx Microprocessor available in GDSII Hardcore, RTL Softcore, and FPGA Specific Firm Cores.
High-performance, commercial-grade RISC-V CPU Core IP
Commercial-grade 64-bit RISC-V CPU IP that is RVA23 Profile compliant, supports Vector and Vector Crypto extensions, and enables high-performance applications.
Hardware link (de)compression IP for die-to-die, chip-to-chip, and DRAM interfaces
Expands effective bandwidth across links and memory interfaces with deterministic, data-independent latency, fully pipelined to sustain line rate
High performance-efficient edge deep learning accelerator for small LLM/VLM/VLA and CNN/RNN/LSTM
Clustered IP to Scale Throughput
When one engine isn’t enough, Atrevido Cluster multiplies throughput under the same ISA and memory‑first design (CPU/Vector, optionally Tensor‑equipped instances)
Scaled for heavier inference and higher throughput
C1 is a compact, fully programmable RISC‑V AI IP core for real‑time inference
Single 1024-bit SIMD DSP for Vision/Radar/Lidar/AI
These cores implement a Bose-Chaudhuri-Hocquenghem (BCH) error correction code configured to process a k-bit codeword, providing …
10xEngineers Debug & N-Trace IP delivers a unified Debug + Trace solution that provides full-system visibility with low overhead …
5G LDPC Decoder
5G Polar Decoder
4G/5G Dual Mode Cell Search
LTE Turbo Decoder
LTE Viterbi Decoder
eFPGA IP — Flexible Reconfigurable Logic Acceleration Core
RapidFlex eFPGA IP provides a reconfigurable, upgradeable, and iterative logic computing layer for SoCs, MCUs, AI accelerators, i…
Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
Maximum performance for running Linux high-end applications.