Vendor: Zipcores Electronic Systems Engineering S.L. Category: Arithmetic Units

Pipelined Multiplier with generic width and depth

PIPE_MULT is a general purpose multiplier with a configurable data width and configurable number of pipeline stages.

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Overview

PIPE_MULT is a general purpose multiplier with a configurable data width and configurable number of pipeline stages. Input values are accepted as either signed or unsigned numbers depending on the generic setting use_signed. Likewise, output values are either signed or unsigned depending on the same setting.

The number of pipeline stages may be programmed using the generic parameter levels. By changing this value, a multiplier may be generated which trades off latency against maximum attainable clock frequency. In addition, the pipelined multiplier component also includes a compiler hint generic setting. By modifying this setting, the compiler can be instructed to infer LUT-based or hard multiplier/DSP resources.

Values are sampled on the rising clock-edge of clk when en is high. The function has a clock-cycle latency which is equal to the number of pipeline levels.

Key features

  • Synthesizable, technology independent VHDL IP Core
  • Function y = a * b
  • Input values as signed or unsigned numbers
  • Output values as signed or unsigned numbers
  • Configurable data with and pipeline depth
  • Supports both LUT-based or hard multiplier blocks
  • Includes a classic shift-add multiplier for larger width implementations
  • High-speed fully pipelined architecture

Block Diagram

PIPE_MULT block diagram

Applications

  • Fixed-point mathematics
  • Fundamental building block in all digital processing functions

Specifications

Identity

Part Number
PIPE_MULT
Vendor
Zipcores Electronic Systems Engineering S.L.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Zipcores Electronic Systems Engineering S.L.

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Frequently asked questions about Arithmetic Unit IP cores

What is Pipelined Multiplier with generic width and depth?

Pipelined Multiplier with generic width and depth is a Arithmetic Units IP core from Zipcores Electronic Systems Engineering S.L. listed on Semi IP Hub.

How should engineers evaluate this Arithmetic Units?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Arithmetic Units IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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