Pipelined Multiplier with generic width and depth

PIPE_MULT is a general purpose multiplier with a configurable data width and configurable number of pipeline stages. Input values are accepted as either signed or unsigned numbers depending on the generic setting use_signed. Likewise, output values are either signed or unsigned depending on the same setting.

The number of pipeline stages may be programmed using the generic parameter levels. By changing this value, a multiplier may be generated which trades off latency against maximum attainable clock frequency. In addition, the pipelined multiplier component also includes a compiler hint generic setting. By modifying this setting, the compiler can be instructed to infer LUT-based or hard multiplier/DSP resources.

Values are sampled on the rising clock-edge of clk when en is high. The function has a clock-cycle latency which is equal to the number of pipeline levels.

• Synthesizable, technology independent VHDL IP Core
• Function y = a * b
• Input values as signed or unsigned numbers
• Output values as signed or unsigned numbers
• Configurable data with and pipeline depth
• Supports both LUT-based or hard multiplier blocks
• Includes a classic shift-add multiplier for larger width implementations
• High-speed fully pipelined architecture

• Fixed-point mathematics
• Fundamental building block in all digital processing functions