SCR4 is a 32/64-bit RISC-V low-power, high-performance, area-optimized processor core with floating-point arithmetic functionalit…
SCR4 is a 32/64-bit RISC-V low-power, high-performance, area-optimized processor core with floating-point arithmetic functionality.
The SCR4 core fully supports RISC-V standard "I" Integer, "M" Integer Multiplication and Division, "A" Atomic, "C" 16-bit Compressed, "F" Single-Precision Floating-Point, "D" Double-Precision Floating-Point, “B” Bit Manipulation, and “K” Scalar Cryptography extensions. SCR4 includes an in-order 5-stage pipeline, a floating-point unit, a branch prediction unit for efficient code execution, separate L1 instruction and data caches, PLIC, ACLINT, IPIC/CLIC units for efficient interrupt processing, and industry-standard AHB, AXI4, JTAG, and cJTAG interfaces increasing flexibility and compatibility.
The SCR4 memory subsystem includes a TCM unit, L1 and L2 caches, an MPU unit and supports seamless execution of various real-time operating systems. The processor core can operate in heterogenous multicore (up to 4 cores in a cluster) environments, offering hardware-level support for memory coherency and simplified external accelerators integration.
SCR4 Key Features
| Core | |
|---|---|
| ISA | RV32/RV64IMCF[ADBK] Atomic Instructions [A], Double-Precision Floating-Point Instructions [D], Bit Manipulation [B], Scalar Cryptography Instructions [K] — optional |
| Pipeline | 3-5 stages |
| Floating-Point Unit (FPU) | Single/Double-precision, IEEE 754-2008 standard |
| Multicore Support (SMP) | Up to 4 cores with cache coherency |
| Branch Prediction Unit (BPU) | Static/Dynamic |
| Memory Subsystem | |
| Tightly-Coupled Memory (TCM) | Up to 256KB, error protection — parity/ECC |
| L1 Cache | Up to 32KB + 32KB, error protection — parity/ECC |
| L2 Cache | From 128KB to 512KB, error protection — ECC |
| Memory Protection Unit (MPU) | Configurable, up to 32-region MPU |
| Interrupt Subsystem | |
| IPIC | Up to 32 interrupt lines |
| CLIC | Up to 4096 interrupt lines, up to 256 priority levels |
| PLIC | Up to 1023 interrupt lines, up to 256 priority levels |
| ACLINT | Up to 4096 interrupt lines |
| Debug Subsystem | |
| Interface | JTAG/cJTAG-compliant interface |
| Breakpoints | Up to 8 hardware breakpoints, unlimited software breakpoints support |
| Interfaces | |
| AXI | Master AXI4 AMBA standard interface |
| AHB | Master AHB AMBA standard interface |
| Timers and Counters | |
| Performance Monitoring | Up to 32 performance counters |
| Embedded 64-bit RTC Timer | Machine-mode timer interrupt support |
Development Tools
Syntacore Development Toolkit (SCR4 Optimized)
The SC-DT package is a ready-to-use software development kit containing pre-built and pre-configured tools that simplify software development for the SCR4 core. With SC-DT, you can take advantage of the pre-built tools and configurations to reduce the time and effort required to get up and running with SCR4. SC-DT supports Windows and Linux operating systems and includes:
Syntacore also supports and maintains the Zephyr operating system that is not part of the SC-DT package and is downloadable separately.
SCR4 is available out-of-the-box, configurable, written in SystemVerilog and comes with a full set of pre-built, tested, and optimized development tools, pre-configured FPGA-based SDK and complete documentation. The software package includes ready-to-use toolchains, IDEs, operating systems, bootloaders, debuggers, simulators, and sample projects that reduce the time and effort required to get up and running with SCR4.
The SCR4 product package includes:
Note: some files may require an NDA depending on provider policy.
Efficient microcontroller core with a 5-stage in-order pipeline, privilege modes, an FPU, an MPU, L1 and L2 caches is a MCU IP core from Syntacore listed on Semi IP Hub.
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