Vendor: Cadence Design Systems, Inc. Category: DSP Core

Tensilica Fusion F1 DSP

Smallest and lowest power DSP for narrowband wireless communications and always-on applications The Cadence® Tensilica® Fusion F1…

Overview

Smallest and lowest power DSP for narrowband wireless communications and always-on applications

The Cadence® Tensilica® Fusion F1 DSP offers the lowest energy, small footprint, high-performance control and signal processing best fit for narrowband wireless communication, always-on, IoT, and wearables applications. The Fusion F1 DSP is very efficient in running communications standards typically associated with IoT device communications, such as Bluetooth LE, Thread, and Zigbee using IEEE 802.15.4, SmartGrid 802.15.4g, WiFi 802.11n and 802.11ah, 2G and LTE Category 0 release 12 and 13, and global navigation satellite systems (GNSS). The Fusion F1 DSP also is suitable for designs in voice trigger, voice recognition, face trigger, context-aware sensor fusion, and similar applications.

Key features

  • Certified ISO 26262:2018 ASIL-compliant
  • AES-128 acceleration
  • Viterbi for WiFi and LTE
  • Acceleration for ITU/ETSI voice codec
  • Fixed-point MAC and floating-point FMA
  • Versatile for a broad segment of IoT, wearable, and NB wireless communications designs
  • TIE for easy extension and further performance enhancement
  • Optimized libraries and application examples for easy software development

Block Diagram

Tensilica Fusion F1 DSP block diagram

Applications

  • Automotive,
  • Communications,
  • Consumer Electronics,
  • Data Processing,
  • Industrial and Medical,
  • Military/Civil Aerospace,
  • Others

Specifications

Identity

Part Number
Tensilica Fusion F1 DSP
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about DSP Core IP core

PCI Express Security and TEE Integration, Part 1 - Establishing Trust

Protecting processor memory alone is no longer sufficient. The entire I/O path must become part of the trusted computing architecture. To address this challenge, PCI-SIG® has developed a suite of complementary security technologies, including Data Object Exchange (DOE), Component Measurement and Authentication (CMA), Integrity and Data Encryption (IDE), and the TEE Device Interface Security Protocol (TDISP).

How a Multi-Protocol PHY Simplifies Physical AI Connectivity

Physical AI systems must move large amounts of data across two very different connectivity domains. Accelerators and local storage need high-bandwidth, low-latency links close to the compute SoC, while sensors and control modules require reliable connectivity across the larger platform. Supporting both domains with separate high-speed PHYs can increase silicon area and integration complexity.

Frequently asked questions about DSP Core IP cores

What is Tensilica Fusion F1 DSP?

Tensilica Fusion F1 DSP is a DSP Core IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this DSP Core?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DSP Core IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP