The 32-bit D45-SE is an 8-stage superscalar processor that supports ISO 26262 ASIL (Automotive Safety Integrity Level) -D level f…
- Safety MCU
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
The 32-bit D45-SE is an 8-stage superscalar processor that supports ISO 26262 ASIL (Automotive Safety Integrity Level) -D level f…
The eMMC LDPC Encoder/Decoder is an flash reliability solution engineered to maximize flash endurance and retention.
Australis is the combination of over 30 years of programmable logic experience and expertise with proven standard ASIC design met…
The ARC-V™ RMX-100 series processors are optimized for use in embedded applications where power and area are the utmost concern.
The ARC-V™ RMX-500 Processors are based on the RISC-V instruction set architecture (ISA) and optimized for use in embedded applic…
ARC-V RMX Series Functional Safety Processor IP
The ARC-V™ RMX-110-FS and RMX-510-FS Functional Safety Processors simplify development of safety-critical applications and accele…
GPNPU Processor IP - 1 to 7 TOPs
Designed from the ground up to address significant machine learning (ML) inference deployment challenges facing system on chip (S…
LZ4SNP-D is a custom hardware implementation of a lossless data decompression engine for the LZ4 and Snappy compression algorithm…
Centralised Real Time Processor IP Core
We provide many configurations for our cryptographic solutions based on the requirements of the project.
32-bit CPU IP core - ISO 26262 Automotive Functional Safety Compliant
AndesCore™ D25F-SE is a 32-bit CPU IP core that supports ISO 26262 ASIL B level functional safety for automotive applications.
Accelerate Edge AI Innovation AI data-processing workloads at the edge are already transforming use cases and user experiences.
A CPU Foundation for the Automotive Industry The Arm Neoverse V3AE CPU is built to deliver maximum performance for automotive app…
Neoverse Compute Subsystems N3 (CSS N3)
The Performance-per-Watt Arm Neoverse N3 Platform Validated by Arm for Networking and Edge Markets configurable to target 5G, DPU…
Neoverse Compute Subsystems V3 (CSS V3)
The High-Performance Arm V3 Platform Performance-Optimized and Validated by Arm Arm Neoverse CSS V3 is the fastest path to buildi…
The SCE02C is a very high speed 4 state CCSDS compatible serial concatenated convolutional code (SCCC) encoder with frame marker,…
64-bit RISC-V high-performance embedded core
64-bit RISC-V high-performance embedded core.
32-bit RISC-V compact high-performance embedded core
32-bit RISC-V compact high-performance embedded core.
64-bit RISC-V core with in-order dual issue pipeline based complex for Linux-based systems
64-bit RISC-V core with in-order dual issue pipeline based complex.
Superscalar Out-of-Order Execution Multicore Cluster
AndesCore™ AX65 64-bit multicore CPU IP is a high-performance quad decode 13-stage superscalar out-of-order processor based on An…
The Cadence® Tensilica® NNE 110 offers an energy-efficient hardware-based AI engine that can be paired with a Tensilica based DSP.