Using Tcl to create a virtual component in Verilog

By Randall Melton, Atmel
Embedded.com  (10/02/09, 10:25:00 AM EDT)

It has long been a goal to put realistic prototypes or models into system developer's hands as soon as possible.  This has been accomplished with FPGAs, C language models and sometimes co-simulation with actual design libraries.

The latter is traditionally done with custom written PLI and VPI plugins that allow the running simulation to interact with something outside the simulation environment.  These have the advantage of allowing system development to proceed before the actual silicon is available for a product. 

Used properly such an environment can feed valuable information back to the digital design team about application level issues before the design is committed to silicon. This article will demonstrate a simple technique to accomplish this with commonly available tools, in particular, the TCL scrpting language.

Most digital designs are verified with logic simulation tools.  Those verification suites usually involve large simulation test benches with complex infrastructures to support stimulus timing, expected outputs, and assertions (formal or otherwise).  Many of these test benches are transaction based.  I consider transaction based to mean the test bench sends some quantum of information to the DUT (design under test) and the DUT replies with some quantum of information.

These quanta (call them packets or transactions) could be single bit operations (like a single logic level plus time interval on a USART TX bit) or complex operations involving multiple clock cycles (like a USB packet) Most traditional test benches already have this infrastructure in place (usually done with tasks in Verilog test benches) to deal with the manipulation and transfer of these packets.

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