Using customizable MCUs to bridge the gap between dedicated SoC ASSPs, ASICs and FPGAs: Part 1
By Jay Johnson, Atmel Corp.
Jun 13 2007 (18:15 PM), Embedded.com
Custom ASICs always offer the best performance, power consumption, security and unit cost of any silicon-based solution. Cell-based ASICs provide the best characteristics because the poly and diffusion layers for interconnect, and transistors can be sized to optimize speed, density, and power dissipation according to each particular cell's requirements.
This approach provides for a silicon-efficient design, but is expensive because it requires a full mask set. Mask costs increase sharply with shrinking process technology or feature size.
Indeed, the $250,000+ cost of a full 130 nm mask set and the lengthy design time associated with standard cell ASICs puts them out of reach for many products. In fact, in applications such as MP3 players or cell phones, the technology evolves so rapidly that the next generation product must be launched every six months -- about half the time required to implement a cell-based ASIC.
Jun 13 2007 (18:15 PM), Embedded.com
Custom ASICs always offer the best performance, power consumption, security and unit cost of any silicon-based solution. Cell-based ASICs provide the best characteristics because the poly and diffusion layers for interconnect, and transistors can be sized to optimize speed, density, and power dissipation according to each particular cell's requirements.
This approach provides for a silicon-efficient design, but is expensive because it requires a full mask set. Mask costs increase sharply with shrinking process technology or feature size.
Indeed, the $250,000+ cost of a full 130 nm mask set and the lengthy design time associated with standard cell ASICs puts them out of reach for many products. In fact, in applications such as MP3 players or cell phones, the technology evolves so rapidly that the next generation product must be launched every six months -- about half the time required to implement a cell-based ASIC.
To read the full article, click here
Related Semiconductor IP
Related Articles
- Bridging the gap between custom ASICs and ARM-based MCUs
- Implementing custom DDR and DDR2 SDRAM external memory interfaces in FPGAs (part 1)
- Single event effects (SEEs) in FPGAs, ASICs, and processors, part I: impact and analysis
- Performance optimization using smart memory controllers, Part 1
Latest Articles
- LLM Agent-Based Design of RISC-V CPUs with FPGA-in-the-Loop Evaluation
- Automated Multi-Line Bug Repair Using Model Checker Aided LLMs: A Case Study on RISC-V Processors
- Cryogenic Recharacterization of a Commercial 22 nm FD-SOI Foundry Standard-Cell Library
- A 105 MS/s 4.18 nJ/inference 0.765 mm² Mixed-Signal Streaming ML Engine for Wireless Baseband in 12LP+ FinFET
- Agentic AI for Heterogeneous System Design Across Chip, Scale-Up, and Scale-Out Domains