NoCs and the transition to multi-die systems using chiplets
By Ashley Stevens, Arteris
EDN (August 2, 2024)
Monolithic dies have long been used in integrated circuit (IC) design, offering a compact and efficient solution for building application-specific integrated circuits (ASICs), application-specific standard parts (ASSPs) and systems-on-chip (SoCs). Traditionally favored for simplicity and cost-effectiveness, these single-die systems have driven the semiconductor industry’s advancements for decades.
However, as the demand for more powerful and versatile technology grows, the limitations of monolithic dies, particularly in terms of scalability and yield, become increasingly significant. This challenge has prompted a shift toward multi-die systems using chiplets.
Emerging trends in multi-die systems
The semiconductor industry is shifting toward multi-die architectures using chiplets to enable more flexible, scalable, and efficient designs. This transition involves a change in physical architecture and collaborative innovation among various ecosystem players to integrate diverse technologies into a single system.
To read the full article, click here
Related Semiconductor IP
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- NoC Interconnect IP Generator
- NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
- NoC Verification IP
- FlexGen Smart Network-on-Chip (NoC) IP
Related Articles
- The Hitchhiker's Guide to Programming and Optimizing CXL-Based Heterogeneous Systems
- GenAI for Systems: Recurring Challenges and Design Principles from Software to Silicon
- Using audio codecs IP as the digital audio hub in mobile multimedia systems
- Design trade-offs of using SAR and Sigma Delta Converters for Multiplexed Data Acquisition Systems
Latest Articles
- FlexSpIM: An Event-Based Digital Compute-In-Memory Accelerator with Flexible Operand Resolution and Layer-Wise Hybrid Stationarity
- MeshKV: A Network-on-Chip KV Cache Fabric for Scalable Transformer Decoding Accelerators
- Analog Pin Directionality as an Exfiltration Attack Surface in Mixed-Signal ICs
- SIMT-Aware Lockstep Verification and Functional-Coverage Closure Methodology for an Open-Source RISC-V GPGPU: A UVM 1.2 Environment
- Efficient Hardware Information-Flow Tracking for Pre-Silicon Security Testing