Transitioning to multicore processing
Rob Oshana and Shuai Wang, Freescale Semiconductor
EETimes (8/31/2011 4:13 PM EDT)
Hesitating to make the shift from single- to multiple-core processing in your design? Here's a guide to making the transition.
The transition to multicore processing requires changing the software programming model, scheduling, partitioning, and optimization strategies. Software often requires modifications to divide the workload among cores and accelerators, to use all available processing in the system and maximize performance. Here's how you and your team can make the switch.
Networking systems, for example, normally include control-plane and data-plane software (shown in Figure 1). The control plane is responsible for managing and maintaining protocols (such as OSPF, SNMP, IPSec/IKE) and other special functions such as high-availability processing, hot plug and play, hot swap, and status backup. Control-plane functions include management, configuration, protocol hand-shaking, security, and exceptions. These functions are reliability sensitive but not extremely time sensitive. Normally, control-plane data packets/frames only occupy ~5% of the overall system load.
To read the full article, click here
Related Semiconductor IP
Related Articles
- Putting multicore processing in context: Part One
- Putting Multicore Processing in Context: Part 2
- Transitioning from DDR4 to DDR5 DIMM Buffer Chipsets
- Partitioning to optimize AI inference for multi-core platforms
Latest Articles
- Automated Multi-Line Bug Repair Using Model Checker Aided LLMs: A Case Study on RISC-V Processors
- Cryogenic Recharacterization of a Commercial 22 nm FD-SOI Foundry Standard-Cell Library
- A 105 MS/s 4.18 nJ/inference 0.765 mm² Mixed-Signal Streaming ML Engine for Wireless Baseband in 12LP+ FinFET
- Agentic AI for Heterogeneous System Design Across Chip, Scale-Up, and Scale-Out Domains
- Minimum RISC-V: Maximum FPGA Efficiency