Transitioning from DDR4 to DDR5 DIMM Buffer Chipsets
By Doug Daniels, Rambus
EEWeb, (January 23, 2019)
There are a number of key changes to DDR that introduce new design challenges. However, savvy designers will use the transition time to nail down solutions.
Server and system designers are gearing up to transition from DDR4 to DDR5 server dual-inline memory module (DIMM) buffer chipsets in their upcoming designs. A foremost consideration involves major specification changes. It is expected that designers will focus on the top (most significant) half-dozen of these changes to advance server designs.
Those are the data and clock rate, VDD (or operating voltage), power architecture, channel architecture, burst length, and improvements for higher-capacity DRAM support. These new changes present special design considerations covered in the second part of this article.
To read the full article, click here
Related Semiconductor IP
- MIL-STD-1553 Controller IP
- UFS 5.x Device IP
- UCIe 3.x Controller IP
- Ethernet 800G PCS IP
- CHI to UCIe Bridge IP
Related Articles
- Transitioning from C/C++ to SystemC in high-level design
- Migrating your embedded PCB design from DDR2/3 to DDR4 SDRAMs
- From ADAS to Autonomous Cars: Key Design Lessons
- Analog IP to protect SoC from side-channel attacks
Latest Articles
- CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs