Transitioning from DDR4 to DDR5 DIMM Buffer Chipsets
By Doug Daniels, Rambus
EEWeb, (January 23, 2019)
There are a number of key changes to DDR that introduce new design challenges. However, savvy designers will use the transition time to nail down solutions.
Server and system designers are gearing up to transition from DDR4 to DDR5 server dual-inline memory module (DIMM) buffer chipsets in their upcoming designs. A foremost consideration involves major specification changes. It is expected that designers will focus on the top (most significant) half-dozen of these changes to advance server designs.
Those are the data and clock rate, VDD (or operating voltage), power architecture, channel architecture, burst length, and improvements for higher-capacity DRAM support. These new changes present special design considerations covered in the second part of this article.
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