SoCs' death somewhat exaggerated: panel
SoCs' death somewhat exaggerated: panel
By Brian Fuller, EE Times
March 12, 2003 (4:48 p.m. EST)
URL: http://www.eetimes.com/story/OEG20030311S0037
SCOTTSDALE, Ariz. The system-on-chip methodology may not be dead as some have suggested but its onerous costs are limiting the devices to a few large companies and forcing everyone else to think differently, a panel said Tuesday (March 11). "It's pretty daunting if you do a full-custom SoC," said John Bourgoin, president and CEO of MIPS Technologies Inc. "If you're going to do SOCs you'll need to take advantage of programmability." Bourgoin, Jordan Plofsky, senior vice president at programmable logic vendor Altera,and Peter Hillen, North American president of Korean foundry Dongbu, discussed the future of SoCs during a panel convened for the Semico Summit conference here. That future was called into question last month at a technical conference in San Francisco. Plofsky dissected the often-cited $30 million cost associated with a new SOC design. He said that while mask costs at finer geometries are indeed painfully high, engineering costs have risen more dramatically in the past decade. If masks and wafer costs were more than a third of engineering costs at the 0.35-micron generation, they're down to one-tenth at 130nm and 90 nm, Plofsky said. In addition, the target market has to be at least $1.5 billion for the project to be considered a success, he said. Plofsky used a calculation that assumed the project R&D was 20 percent of revenue and that eventual market share of that $1.5B market would be roughly 10 percent. So the revenue from the project would total $150 million. Turning to the $30.6 billion communications market, Plofsky said there really only two segments of that market that meet this ROI criteria, mobile infrastructure ($2.5 billion) and 10/100 gigabit fixed subsystems ($1.4 billion). The possible target markets expand a little bit more in consumer, computing and industrial sectors but there are no more than a dozen segments within those areas that me et Plofsky's requirements. “The economics of SoC is going to be the limiting factor,” he said. “You're going to see the rise of general-purpose products that can span many markets.” Peter Hillen, North American president of Korean foundry Dongbu, took issue with SoC definitions. “There is an idealized notion of SoC with many technologies on board and that's just not going to be practical,” he said. Smaller-scale SoCs containing a CPU, memory and some mixed-signal circuitry, are much more realistic SoC design candidates, he added.
Related Semiconductor IP
- nQrux® Root of Trust IP
- AXI to UCIe Bridge IP
- UCIe 2.x Controller IP
- SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP
- OpenTitan-based RISC-V Secure Element
Related Articles
- Panel finds many ways to build a platform
- Panel dispels myths of SoC design
- Panel dispels myths of SoC design
- Panel concurs: Designers must deliver complete solutions
Latest Articles
- A Secure dToF LiDAR SoC with Dual-Domain Fingerprinting and Event-Driven AFE Circuit Achieving Sensor-Level Attack Resilience
- ZTA-Q: an Open-source RISC-V Platform for Accurate Quantized CNN Inference
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM