SoC: Codesign and Test -> Complex SoCs breed new design strategies
Complex SoCs breed new design strategies
By Chappell Brown, EE Times
December 22, 2000 (3:28 p.m. EST)
URL: http://www.eetimes.com/story/OEG20001222S0044
The task of building effective system-on-chip (SoC) devices is nudging electronic engineers-whether circuit designers or test and verification specialists-out of their comfortable niches. Trained as specialists, designers are being asked to confront the diverse circuit types that can now coexist on the same chip, essentially forcing them to become generalists. Today, it is no longer enough to be good at, say, logic design, without also having a good grasp of memory types, programmable logic or mixed-signal design. And the various methods of blending software with hardware and the thorny issues of test and verification get thrown into the mix as well. This week's System Design focuses on those SoC issues. Contributors are grappling with the larger issues of how to blend technologies, or in some cases, how to avoid having to blend technologies with new tools and design approaches. "All logic suppliers, driven by the economics of integ ration, are moving toward SoC devices," said Yankin Tanurhan, director of Embedded FPGA at Actel Corp. (Sunnyvale, Calif.). But although integration has always brought many advantages with it, Tanurhan noted that at the more recent complexity scales, and enabled by deep-submicron processes, the design and mask set costs of those devices can skyrocket.
Actel is introducing an embeddable programmable gate array core that blends fast static RAM memory in order to offer a standard design that can meet the needs of diverse ASIC-style design objectives.
With the increasing variety of circuit types on the same chip, the whole area of test and verification is undergoing a revolution. The earlier strategy of building a chip and then testing it has gone out the window, according to Yervant Zorian, chief technology adviser at LogicVision Inc. (San Jose, Calif.). As a result, test a nd verification is being replaced by a more dynamic co-test and co-verification strategy.
Related Semiconductor IP
- LPDDR6 PHY
- UMC 55nm ULP 3.3V Temperature Sensor
- High-Throughput Multi-Channel DMA Controller
- Configurable Multi-Channel DMA Controller
- Fixed-Channel Multi-Channel DMA Controller
Related Articles
- Bigger Chips, More IPs, and Mounting Challenges in Addressing the Growing Complexity of SoC Design
- FPGA Prototyping of Complex SoCs: RTL code migration and debug strategies
- Fully-programmable SoCs -- A new breed of devices
- The Growing Imperative Of Hardware Security Assurance In IP And SoC Design
Latest Articles
- Automated Multi-Line Bug Repair Using Model Checker Aided LLMs: A Case Study on RISC-V Processors
- Cryogenic Recharacterization of a Commercial 22 nm FD-SOI Foundry Standard-Cell Library
- A 105 MS/s 4.18 nJ/inference 0.765 mm² Mixed-Signal Streaming ML Engine for Wireless Baseband in 12LP+ FinFET
- Agentic AI for Heterogeneous System Design Across Chip, Scale-Up, and Scale-Out Domains
- Minimum RISC-V: Maximum FPGA Efficiency