"So, when will you be done with your design?"
Jeroen Fonderie, Touchstone Semiconductor
EDN (March 4, 2013)
Not exactly the question a typical design engineer is looking forward to. You’re at the start of a new project and it is time to commit to a development schedule. Now what? Your first instinct is to be vague. Use verbs like “should” and “hope” and lots of conditional statements. But you know that’s not going to fly. You can give your best estimate. But you’re usually too optimistic and then you will get yelled at when you don’t meet that commitment.
Or you can pad the heck out of it. At least that way you know you will not be bothered for many weeks. But now your manager and your peers may start to see you as a sandbagger whose input is not to be taken seriously. So what is the best way to come up with a schedule for the design phase of your project?
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Articles
- Add Security And Supply Chain Trust To Your ASIC Or SoC With eFPGAs
- 7 warning signs that you should be concerned about your IP provider
- EDA in the Cloud Will be Key to Rapid Innovative SoC Design
- Calibrate and Configure your Power Management IC with NVM IP
Latest Articles
- LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
- A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node
- Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework
- VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration
- CTTE: An Open Dual-Protocol RISC-V Trace Encoder for N-Trace and E-Trace