"So, when will you be done with your design?"
Jeroen Fonderie, Touchstone Semiconductor
EDN (March 4, 2013)
Not exactly the question a typical design engineer is looking forward to. You’re at the start of a new project and it is time to commit to a development schedule. Now what? Your first instinct is to be vague. Use verbs like “should” and “hope” and lots of conditional statements. But you know that’s not going to fly. You can give your best estimate. But you’re usually too optimistic and then you will get yelled at when you don’t meet that commitment.
Or you can pad the heck out of it. At least that way you know you will not be bothered for many weeks. But now your manager and your peers may start to see you as a sandbagger whose input is not to be taken seriously. So what is the best way to come up with a schedule for the design phase of your project?
To read the full article, click here
Related Semiconductor IP
- Zigbee Transceiver PHY
- Data Flow Architecture IP
- AMBA SPI Controller MRAM Controller
- Ethernet MAC
- Protocol Bridges
Related Articles
- Add Security And Supply Chain Trust To Your ASIC Or SoC With eFPGAs
- 7 warning signs that you should be concerned about your IP provider
- EDA in the Cloud Will be Key to Rapid Innovative SoC Design
- Calibrate and Configure your Power Management IC with NVM IP
Latest Articles
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection
- BitFair: A 12nm Bit-Serial CNN Accelerator with Learnable Early Termination and Adaptive Bit Ordering for Ultra-Low-Power XR Vision
- A Flexible Sparsity-Aware FPGA Accelerator with Column-Wise Compression for Efficient CNN Inference
- Reducing Instruction-Fetch Energy in RISC-V for Embedded AI Processing via Dynamic and Static Loop Caching
- SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow