Silicon segmentation

You have a diverse set of silicon resources to choose from, and vendors are tailoring their building-block portfolios to meet your needs.

By Brian Dipert, Technical Editor -- EDN, 9/18/2003

So, you've decided that buying and hooking together off-the-shelf ASSPs (application-specific standard products), such as embedded controllers, peripheral chips, and the like, and then writing your own software, will fail to provide your design sufficient differentiation from competitors' products. As a result, you elect to tackle chip-level design. The two leading silicon-platform contenders and their respective trade-offs have by this time been extensively debated in a variety of industry forums, but if you're new to the game, here's a summary.

Related Semiconductor IP

AXI to UCIe FDI Interface IP
45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
Peripheral Sensor Interface (PSI5) Host Controller
Link Acceleration Unit

Reconfiguring Design -> Adaptive computing makes efficient use of silicon
Retargeting IP -> Silicon prototyping verifies IP functions
Retargeting IP -> Design system compiles silicon straight from C code
IP vendors making leap from source code to silicon

Latest Articles

Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
LLM4RTL: Tool-Assisted LLM for RTL Generation
Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs
CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety

Silicon segmentation

Subscribe to the Semi IP Hub Newsletter

Related Semiconductor IP

Related Articles

Latest Articles