Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes

By Lorenzo Ruotolo ^1, 4, Lara Orlandic ², Pengbo Yu ², Moritz Brunion ⁴, Daniele Jahier Pagliari ¹, Dwaipayan Biswas ⁴, Giovanni Ansaloni ², David Atienza ², Julien Ryckaert ⁴, Francky Catthoor ³, and  Yukai Chen ^4
1 Politecnico di Torino, Italy
² Ecole Polytechnique Fédérale de Lausanne (EPFL), Switzerland
³ National Technical University of Athens, Greece
⁴ IMEC, Belgium

Abstract

This paper presents the physical design exploration of a domain-specific processor (DSIP) architecture targeted at machine learning (ML), addressing the challenges of interconnect efficiency in advanced Angstrom-era technologies. The design emphasizes reduced wire length and high core density by utilizing specialized memory structures and SIMD (Single Instruction, Multiple Data) units. Five configurations are synthesized and evaluated using the IMEC A10 nanosheet node PDK. Key physical design metrics are compared across configurations and against VWR2A, a state-of-the-art (SoA) DSIP baseline. Results show that our architecture achieves over 2x lower normalized wire length and more than 3x higher density than the SoA, with low variability in the metrics across all configurations, making it a promising solution for next-generation DSIP designs. These improvements are achieved with minimal manual layout intervention, demonstrating the architecture's intrinsic physical efficiency and potential for low-cost wire-friendly implementation.

Index Terms—domain-specific processors, machine learning, physical design, nanosheet, wirelength optimization.

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