Optimizing efficiency and flexibility in DSP systems
Mouna Elkhatib and Sverrir Olafsson, Conexant
EDN (January 13, 2013)
For as long as multipliers have been implemented in silicon, DSP (digital signal processing) devices have been developed to solve problems in audio, video, communications and a variety of other applications. In many cases the DSP algorithms have been implemented directly in dedicated customized logic to achieve an optimal solution. In others, generic programmable DSPs have been utilized to provide a flexible platform to implement algorithms in firmware. Increasingly, GPPs (general purpose processors) and CPUs (central processing units) have acquired capabilities to realize DSP algorithms, offering a platform to mix non-DSP functions like network stacks with complex DSP algorithms on the same CPU.
This article will explore the tradeoffs leading designers to these different design choices. Typically, well understood algorithms of limited complexity are implemented in dedicated hardware, whereas less rigid complex algorithms requiring multiple algorithm steps are implemented on programmable DSPs. If the application requires non-DSP algorithms, such as USB or network protocols, the choice becomes between a GPP and a DSP, where the ratio of DSP calculations to generic (e.g. protocol) computation will typically determine the outcome.
To read the full article, click here
Related Semiconductor IP
- Vision 341 DSP
- Tensilica HiFi 3z DSP
- Tensilica HiFi 4 DSP
- High performance dual-issue, out-of-order, 7-stage Vector processor (DSP) IP
- Versatile, Ultra-Low-Power DSP for Audio, Voice, Vision, and AI
Related Articles
- The Hitchhiker's Guide to Programming and Optimizing CXL-Based Heterogeneous Systems
- How a Standardized Approach Can Accelerate Development of Safety and Security in Automotive Imaging Systems
- Balancing Power and Performance With Task Dependencies in Multi-Core Systems
- High-Performance DSPs -> Reconfigurable coprocessors create flexibility in DSP apps
Latest Articles
- LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
- A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node
- Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework
- VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration
- CTTE: An Open Dual-Protocol RISC-V Trace Encoder for N-Trace and E-Trace