Balancing Power and Performance With Task Dependencies in Multi-Core Systems
By Gokhan Akgun and Diana Göhringer
Technische Universität Dresden, Germany
Abstract:
The increasing use of FPGAs necessitates energy-efficient solutions, particularly for battery-powered applications. Although power dissipation is often perceived as a hardware issue, it can be mitigated through power-saving techniques such as dynamic voltage and frequency scaling and clock gating. In real-time systems, these strategies must reduce the power consumption and meet strict timing requirements to avoid deadline violations. However, hardware constraints and variability in execution times complicate their implementation, particularly in multi-core systems where task dependencies and inter-processor communication introduce delays and unpredictability. Real-time Operating Systems (RTOSs) manage task execution using scheduling algorithms, periodically checking task queues during context switches. Incoming messages trigger sporadic tasks that the RTOS must prioritize immediately, while regular tasks are executed, or power-saving strategies are applied during idle phases. Handling these diverse tasks in multi-core systems adds complexity, making it challenging to balance between predictability, energy efficiency, and system performance. This work introduces a heterogeneous multi-core architecture that integrates power-aware task scheduling algorithms, such as the Look-Ahead algorithm or Race-to-Idle strategy, to optimize power consumption while addressing task dependencies and inter-core communication. A hardware-based task scheduler improves scheduling performance and predictability, while tasks leverage the reconfigurable capabilities of FPGAs and are executed as hardware accelerators to further enhance energy efficiency. The experimental results demonstrate an improvement in scheduling performance of 64.91% and energy efficiency of 92% compared to a baseline without power optimization, highlighting the effectiveness of the proposed approach.
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Articles
- A RISC-V Multicore and GPU SoC Platform with a Qualifiable Software Stack for Safety Critical Systems
- Achieving Lower Power, Better Performance, And Optimized Wire Length In Advanced SoC Designs
- How silicon and circuit optimizations help FPGAs offer lower size, power and cost in video bridging applications
- Real-Time ESD Monitoring and Control in Semiconductor Manufacturing Environments With Silicon Chip of ESD Event Detection
Latest Articles
- LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
- A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node
- Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework
- VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration
- CTTE: An Open Dual-Protocol RISC-V Trace Encoder for N-Trace and E-Trace