New Embedded DRAM Solutions for High-Performance SoCs
by Hideya Horikawa and Hamid Aslam
New leading-edge applications ranging from games to networking infrastructure equipment are driving the need to include large-capacity and high-speed memory on-chip rather than separately as a discrete device. On-chip memory devices enable throughput capabilities into the gigabit-per-second range, as well as compact designs with modest power dissipation and smaller footprints in office, industrial equipment and lightweight electronic devices.
The semiconductor industry is meeting the demands presented by these market trends with system-on-a-chip (SoC) designs. SoCs contain the processor, logic, analog macros and memory needed to perform all of the critical functions; they also represent a major departure from previous system-on-a-board development. In this new, highly integrated chip landscape, innovative solutions for embedded memory are being addressed.
New leading-edge applications ranging from games to networking infrastructure equipment are driving the need to include large-capacity and high-speed memory on-chip rather than separately as a discrete device. On-chip memory devices enable throughput capabilities into the gigabit-per-second range, as well as compact designs with modest power dissipation and smaller footprints in office, industrial equipment and lightweight electronic devices.
The semiconductor industry is meeting the demands presented by these market trends with system-on-a-chip (SoC) designs. SoCs contain the processor, logic, analog macros and memory needed to perform all of the critical functions; they also represent a major departure from previous system-on-a-board development. In this new, highly integrated chip landscape, innovative solutions for embedded memory are being addressed.
Related Semiconductor IP
- MIL-STD-1553 Controller IP
- UFS 5.x Device IP
- UCIe 3.x Controller IP
- Ethernet 800G PCS IP
- CHI to UCIe Bridge IP
Related Articles
- Enabling High Performance SoCs Through Multi-Die Re-use
- Building high performance interrupt responses into an embedded SoC design
- PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
- NetComposer-II: High performance Structured ASIC Programmable NPU platform for layer 4-7 applications
Latest Articles
- CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs