Building high performance interrupt responses into an embedded SoC design

Neha Srivastava, Nitin Goel, Aashish Mittal, and Amitav Halder, Freescale Semiconductor
embedded.com (August 25, 2013)

During normal operations, executing interrupt service routines (ISRs) using conventional approaches requires tight coordination between the system’s interrupt controller (INTC) and the core processor. In such cases the peripheral function’s interrupt requests are handled through the INTC, which collects all of the interrupts and passes them to the core processor, which then stores the ISRs in a status register on stack, after which it finally services the ISR.

During the design of a system-on-chip (SoC), however, verification of both hardware and software functionality can be problematic. Because additional IP blocks have been added for silicon testing purposes, more system clock cycles than normal are required, limiting the ability to exhaustively test the device.

To understand why this occurs, let’s consider a scenario in which an analog-to-digital convertor (ADC) is doing data conversion serially on its 16 channels with the aim of switching to another mode of operation (e.g., injected mode) in the middle of on-going conversion once we receive an interrupt from another IP, say a periodic interrupt timer.

In such a scenario, due to cumulative software delays latency in interrupt servicing as well as inability of the behavioral model to mimic actual analog behavior causes interruptions. By the time the core reaches actual execution of the ISR code, the first conversion is already over and the switch to new mode occurs in the middle of an ongoing conversion and cannot be made. As a result, even though it is a valid use-case in the SoC it is non-targetable through RTL simulation.

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