Multi-Die SoCs Gaining Strength with Introduction of UCIe
By Manuel Mota, Sr. Product Marketing Manager, Synopsys
The Universal Chiplet Interconnect Express UCIe specification brings together very competitive performance advantages to multi-die system designers, including high energy-efficiency, high edge usage efficiency and low latency, and more. Read this article to learn all about UCIe and its many advantages for multi-die system designs.
To read the full article, click here
Related Semiconductor IP
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
Related Articles
- Enabling High Performance SoCs Through Multi-Die Re-use
- Make SoCs flexible with embedded FPGA
- Bulletproofing PCIe-based SoCs with Advanced Reliability, Availability, Serviceability (RAS) Mechanisms
- Revolutionizing Consumer Electronics with the power of AI Integration
Latest Articles
- SCENIC: Stream Computation-Enhanced SmartNIC
- Agentic AI-based Coverage Closure for Formal Verification
- Microarchitectural Co-Optimization for Sustained Throughput of RISC-V Multi-Lane Chaining Vector Processors
- RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
- Emulation-based System-on-Chip Security Verification: Challenges and Opportunities