Make SoCs flexible with embedded FPGA
Geoff Tate, Flex Logix
EDN (November 30, 2016)
Systems designers have long sought to provide programmability and flexibility in their systems designs to meet varying customer needs and evolving standards. The two most common approaches - FPGAs and MPUs/MCUs - provide different kinds of capabilities and complement each other, but have typically been separate devices. Now, chips with both processors and embedded FPGA are becoming a design option.
With the growth of connectivity, information, and data, there is a growing need for new processing capabilities that can span from ultra-low power <$1 microcontrollers to very large networking chips. Moore’s Law has given rise to the availability of new SoCs and MCUs for existing and new markets with each one of these SoCs/MCUs designed specifically for the market segment it is being targeted. This widespread use of special-purpose architectures greatly increases the need for new designs, however, and the rise of new markets (e.g., IoT) and device types (e.g., sensors) for these new markets is growing faster than the SoC types available.
To read the full article, click here
Related Semiconductor IP
- eFPGA IP — Flexible Reconfigurable Logic Acceleration Core
- Radiation-Hardened eFPGA
- eFPGA Hard IP Generator
- eFPGA Soft IP
- eFPGA on GlobalFoundries GF12LPP
Related Articles
- A Flexible Sparsity-Aware FPGA Accelerator with Column-Wise Compression for Efficient CNN Inference
- Designing embedded SoCs using older resistive technologies
- Embedded FPGA: Changing the Way Chips Are Designed
- Bulletproofing PCIe-based SoCs with Advanced Reliability, Availability, Serviceability (RAS) Mechanisms
Latest Articles
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection
- BitFair: A 12nm Bit-Serial CNN Accelerator with Learnable Early Termination and Adaptive Bit Ordering for Ultra-Low-Power XR Vision
- A Flexible Sparsity-Aware FPGA Accelerator with Column-Wise Compression for Efficient CNN Inference
- Reducing Instruction-Fetch Energy in RISC-V for Embedded AI Processing via Dynamic and Static Loop Caching
- SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow