Media SoC design for reduced power consumption

Architectures that are ''power conscious'' use design techniques to reduce the overall gate count and power consumption while efficiently handling data transactions.

By Shinya Fujimoto
Principal Architect, Consumer Products Group, LSI Logic
November 24, 2006

As semiconductor process technologies have advanced enabling designers to pack multi-millions of gates and complex mixed-signal components into a single chip, it has come to a point where designers now need to make smart trade-offs between the SoC's functionality and power consumption.

With the wide variety of IP available to designers, it has become much easier to integrate more features into a single chip than was possible just a few years ago. However, because of the high integration and advanced performance requirements, the chip might consume more power than the system can tolerate. In that case, the designer may have to sacrifice some of the features or reduce the performance to meet the power consumption goals.

Traditionally, power has been a main concern for portable products because they are battery powered. However, the increased power consumption of highly integrated SoCs and the cost pressures in the consumer electronics market is causing system designers of AC powered devices to reduce power consumption so that less expensive chip packaging and simpler heat dissipation systems can be used.

To achieve high integration and simultaneously reduce the overall system power consumption, the SoC needs to be designed with architectures that are "power conscious" which use design techniques to reduce the overall gate count and power consumption while efficiently handling data transactions to minimize inefficient, power consuming interactions with external memory.

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