Interfacing QDR-II+ Synchronous SRAM with high-speed FPGAs, part 2
Reshmi Ravindran, Cypress Semiconductor
EETimes (9/17/2012 3:36 PM EDT)
Part 1 of this article discussed the hardware aspects required for interfacing QDRII+ memory with an FPGA. Part 2 deals with implementation of the QDR II+ controller in popular FPGAs using standard IP blocks.
Implementation of memory interfaces on FPGAs, especially for high-speed memories, was a tedious process until most of the FPGA vendors started providing configurable memory controller IP, such as the Xilinx Memory Interface Generator (MIG) tool and Alteraâs QDR controller Megacore functions. These IP libraries are expensive and are not available with all variants of the FPGAs, however. Fortunately, alternatives exist. Most high-speed FPGAs offer standard IP blocks that can be configured and integrated to build a custom memory controller. This enables designers to develop memory controllers for their application and allows them to customize it suitably. Understanding the timing diagram of QDRII+ is essential for the controller implementation. Letâs take a closer look.
To read the full article, click here
Related Semiconductor IP
- SRAM Memory Model
- QDR II SRAM Controller Intel® FPGA IP Function
- QDR II SRAM Controller Intel® FPGA IP
- ZBT SRAM memory controller
- SRAM Test Solution
Related Articles
- Choosing the right synchronous SRAM for your application
- Growing demand for high-speed data in consumer devices gives rise to new generation of low-end FPGAs
- Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
- A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node
Latest Articles
- FlexSpIM: An Event-Based Digital Compute-In-Memory Accelerator with Flexible Operand Resolution and Layer-Wise Hybrid Stationarity
- MeshKV: A Network-on-Chip KV Cache Fabric for Scalable Transformer Decoding Accelerators
- Analog Pin Directionality as an Exfiltration Attack Surface in Mixed-Signal ICs
- SIMT-Aware Lockstep Verification and Functional-Coverage Closure Methodology for an Open-Source RISC-V GPGPU: A UVM 1.2 Environment
- Efficient Hardware Information-Flow Tracking for Pre-Silicon Security Testing