A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node

By Po-Chuan Wang ¹, Dongwon Jang ¹, Eknath Sarkar ¹, Alexei Svizhenko ², Md. Nahid Haque Shazon ¹, Piyush Kumar ¹, Suman Datta ¹, and Azad Naeemi ^1
1 School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332, USA.
² Synopsys, Sunnyvale, CA 94085, USA.

Abstract

We propose a monolithic-3D (M3D) 6T SRAM at the 2nm node, integrating BEOL IGO pass-gates (PGs) with an all-silicon nanosheet latch, buried power rails (BPRs), and Ru interconnects. TCAD calibrated to a state-of-the-art double-gate IGO transistor with a tri-layer HfO₂/ZrO₂/HfO₂ (HZH) gate stack is combined with virtual fabrication and 3D parasitic extraction to realize the first process-aware layout of this topology. A novel neighbor-cell shared source/drain (S/D) bitline (BL) design enlarges the IGO contact area to mitigate contact resistance and restore PG drive without area penalty. The resulting cell achieves a 25% footprint reduction vs the high-performance (HP) 122 Si baseline while maintaining robust static noise margin (SNM) over a wide supply voltage range. At the 128×256 subarray-level, it reduces write delay by 42.2% and EDP by 9.7% compared to the high-density (HD) 111 Si baseline, owing to reduced cell parasitics and wordline (WL) loading from the smaller footprint.

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