Improving performance and security in IoT wearables
By Pritesh Mandaliya, Cypress Semiconductor
Many IoT applications – including connected cars, factory automation, smart city, connected health, and wearables – require nonvolatile memory to store data and code. Traditionally, embedded applications have used external Flash memory for this purpose.
However, as modern semiconductor technology faces challenges in scaling and cost as it moves to smaller geometries, it has become increasingly difficult to embed Flash memory within the host SoC. Therefore, future MCU or SoC designs are targeting system-in-package (SiP) or the use of external Flash. This trend does not address the needs of IoT applications like wearables because of their small form factor, strict cost constraints, and low-power related requirements.
To address these issues, Flash memory manufacturers are developing architectures that optimize size and power consumption. At the same time, they are introducing important new capabilities that support greater endurance, reliability, security, and safety.
To read the full article, click here
Related Semiconductor IP
- 64-bit, RISC-V, ultra-high performance processors
- 64-bit, RISC-V, performance and data computation processors
- 32-bit, RISC-V, deeply embedded processors
- Verification IP for eUSB 2 v2 and USB 2.0
- AFDX 1G Switch IP
Related Articles
- How to achieve better IoT security in Wi-Fi modules
- The Growing Imperative Of Hardware Security Assurance In IP And SoC Design
- Achieving Lower Power, Better Performance, And Optimized Wire Length In Advanced SoC Designs
- How a Standardized Approach Can Accelerate Development of Safety and Security in Automotive Imaging Systems
Latest Articles
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs
- CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety
- AIA: A 16nm Multicore SoC for Approximate Inference Acceleration Exploiting Non-normalized Knuth-Yao Sampling and Inter-Core Register Sharing