Vendor:
Sofics
Category:
ESD Protection
TSMC 2nm 1V8 ESD Local Clamp – Low Leakage
Silicon-proven ESD protection for GAA/nanosheet technologies
Overview
This specific IP macro is designed in TSMC 2nm and can be ported to other technologies upon request using Sofics in-house design tool flow.
This ESD protection IP provides robust on-chip protection for sensitive supply, and interface pins while minimizing impact on signal performance, leakage, and silicon area. The solution is designed for integration in multiple process nodes and can be adapted to specific interface requirements, voltage domains, and foundry design rules.
The protection concept supports reliable operation under HBM and CDM stress conditions and can be customized for higher robustness levels, low-capacitance interfaces, low-leakage applications, or reduced-area.
Key Features
| Parameter | Value |
|---|---|
| Leakage | <105nA |
| Capacitance | <267fF |
| TLP | 4.17A |
| HBM | 6.25kV |
| CDM | 8.14A |
Area
| Type | Size [μm²] |
|---|---|
| Power | 1646.3 |
Key features
- Silicon-proven ESD protection for GAA/nanosheet technologies
- High robustness against HBM, CDM, latch-up and system-level stress conditions
- Low parasitic capacitance
- Compact layout footprint compared to conventional foundry ESD solutions
- Customizable trigger, holding voltage, leakage and clamp configuration
- Modular design enables fast and reliable turnaround and low NRE
Block Diagram
Click to open fullscreen
Benefits
- Local protection for I/O / analog / RF pins
- Supports HBM and CDM robustness targets
- Optional support for IEC / EOS / EMC
- Low-capacitance implementation
- Low-leakage options available
- Compact ESD clamp layout
- Horizontal and Vertical orientation
- Compatible with foundry or custom pad ring integration
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 2nm | N2P | Available on request |
Specifications
Identity
Part Number
DS-TS2-1V8-LC-LL-ESD
Vendor
Sofics
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Belgium
Learn more about ESD Protection IP core
Breakthrough in area efficiency of on-chip ESD protection
Bart Keppens, Sofics
Selecting optimized ESD protection for CMOS image sensors
Bart Keppens, Sofics
Optimized on-chip ESD protection to enable high-speed Ethernet speed in cars
Bart Keppens, Sofics
Breaking the Bandwidth Barrier: Enabling Celestial AI’s Photonic Fabric™ with Custom ESD IP on TSMC’s 5nm Platform
As AI workloads scale exponentially, bandwidth has become the new bottleneck. This article explores how Celestial AI’s Photonic Fabric™ redefines interconnect performance, and how Sofics’ low-cap ESD and power clamp IP enabled its integration on TSMC’s 5nm platform.
EOS protection characterization using Long-Pulse TLP
EOS, or Electrical Overstress, is a significant factor in IC reliability. Sometimes, IC interfaces and/or power pads are subjected to voltage/current levels beyond the absolute maximum rating. Sources claim that more than 40% of the field failures in electronic products are related to EOS.
Frequently asked questions about ESD Protection Library IP cores
What is TSMC 2nm 1V8 ESD Local Clamp – Low Leakage?
TSMC 2nm 1V8 ESD Local Clamp – Low Leakage is a ESD Protection IP core from Sofics listed on Semi IP Hub. It is listed with support for tsmc Available on request.
How should engineers evaluate this ESD Protection?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this ESD Protection IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.