IC mixed-mode verification: The Sandwiched-SPICE approach
Garima Jain (Freescale)
EDN -- October 21, 2014
RTL- and SPICE-based mixed-signal verification means picking SPICE view for a number of modules (those involved in the concerned test case), and behavioral models for the remaining modules. As analog front-end modules get more complex, AMS verification has become even more challenging.
The limitations to be considered are as follows:
- The number of transistors the module taken in SPICE can have, or,
- The number of fast toggling signals (high frequency clocks etc.) which can be in the module to have reasonable run time.
The case may be such that the number of transistors is acceptable and there are just a couple of fast toggling signals. But what if this is not so? What if the number of fast toggling signals is large, or the netlist size of the module whose SPICE view is being picked is large, or both?
To read the full article, click here
Related Semiconductor IP
- Mesochronous Bridge for PCIe/CXL
- AI-native GPU
- OpenGMSL Verification IP
- OpenGMSL Leaf IP
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
Related Articles
- IC design: A short primer on the formal methods-based verification
- Leveraging UVM based UFS Test Suite approach for Accelerated Functional Verification of JEDEC UFS IP
- A formal-based approach for efficient RISC-V processor verification
- It's Just a Jump to the Left, Right? Shift Left in IC Design Enablement
Latest Articles
- FlexSpIM: An Event-Based Digital Compute-In-Memory Accelerator with Flexible Operand Resolution and Layer-Wise Hybrid Stationarity
- MeshKV: A Network-on-Chip KV Cache Fabric for Scalable Transformer Decoding Accelerators
- Analog Pin Directionality as an Exfiltration Attack Surface in Mixed-Signal ICs
- SIMT-Aware Lockstep Verification and Functional-Coverage Closure Methodology for an Open-Source RISC-V GPGPU: A UVM 1.2 Environment
- Efficient Hardware Information-Flow Tracking for Pre-Silicon Security Testing