IC mixed-mode verification: The Sandwiched-SPICE approach
Garima Jain (Freescale)
EDN -- October 21, 2014
RTL- and SPICE-based mixed-signal verification means picking SPICE view for a number of modules (those involved in the concerned test case), and behavioral models for the remaining modules. As analog front-end modules get more complex, AMS verification has become even more challenging.
The limitations to be considered are as follows:
- The number of transistors the module taken in SPICE can have, or,
- The number of fast toggling signals (high frequency clocks etc.) which can be in the module to have reasonable run time.
The case may be such that the number of transistors is acceptable and there are just a couple of fast toggling signals. But what if this is not so? What if the number of fast toggling signals is large, or the netlist size of the module whose SPICE view is being picked is large, or both?
To read the full article, click here
Related Semiconductor IP
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
- NVMe Validation Test Suite
- Hybrid Memory Cube Verification IP
Related Articles
- IC design: A short primer on the formal methods-based verification
- Leveraging UVM based UFS Test Suite approach for Accelerated Functional Verification of JEDEC UFS IP
- A formal-based approach for efficient RISC-V processor verification
- It's Just a Jump to the Left, Right? Shift Left in IC Design Enablement
Latest Articles
- Terracotta: Enabling the Adoption of New DRAM Techniques via a Flexible DRAM Interface and Memory Controller
- A Framework for Accelerating Transformer Inference on RISC-V for Edge AI
- An Interleaved Parallel Dependent Quantization Hardware Architecture for H.266/VVC
- A Formal Security Analysis of CAN XL
- A Secure dToF LiDAR SoC with Dual-Domain Fingerprinting and Event-Driven AFE Circuit Achieving Sensor-Level Attack Resilience