IC design: A short primer on the formal methods-based verification
by Ashish Darbari, Axiomise
It’s no secret that hardware is the new currency in the chip world. It’s no longer the case that the semiconductor industry is in the hands of traditional semiconductor giants; an increasing number of software companies now have their own dedicated hardware development teams. With the advent of open-source architectures, developing silicon with open-source framework and tools is slowly becoming mainstream.
However, while designing has become easier, verification has not.
The 2020 Wilson Research Group study on functional verification points out that 83% of the FPGA and 68% of the ASIC designs fail in the first attempt. Also worth noting is that 68% of the ASIC projects run behind schedule.
The survey reports that for processor development, the ratio of verification to design engineers is 5:1. Imagine having to hire five times more verification resources than design and having to respin the chip.
To read the full article, click here
Related Semiconductor IP
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
- NVMe Validation Test Suite
- Hybrid Memory Cube Verification IP
Related Articles
- A Survey on the Design, Detection, and Prevention of Pre-Silicon Hardware Trojans
- A short primer on instruction set architecture
- It's Just a Jump to the Left, Right? Shift Left in IC Design Enablement
- A Survey on SoC Security Verification Methods at the Pre-silicon Stage
Latest Articles
- Anechoic: Onsager-Corrected Parallel Annealing for Sub-0.1 ms Dense Max-Cut on an FPGA
- Power, Performance, and Area of HPC-Based Malware Detectors: An FPGA and Open-PDK ASIC Study
- Terracotta: Enabling the Adoption of New DRAM Techniques via a Flexible DRAM Interface and Memory Controller
- A Framework for Accelerating Transformer Inference on RISC-V for Edge AI
- An Interleaved Parallel Dependent Quantization Hardware Architecture for H.266/VVC