Out of the Verification Crisis: Improving RTL Quality

By Harry D. Foster, Siemens EDA (September 15, 2021)

A verification crisis is upon us that requires a holistic and philosophical change in the way we approach design, with a foundation based on bug prevention. A first step in implementing this change is to reduce bug density through a design process that incorporates intent-focused insight. This will have a positive impact on downstream processes and consequently reduces cost.

The crisis

In 1997, Sematech set off an alarm in the industry when it warned that IC manufacturing productivity gains were increasing at a 40% CAGR, while IC design productivity gains increased at only a 20% CAGR. This concern was reiterated in the International Technology Roadmap for Semiconductors 1999 report. Despite these alarms concerning the gap between silicon capacity and design capabilities, the industry avoided this crisis. Why? There were two primary contributors that prevented the design productivity gap: (1) continual improvements in design automation and (2) the emergence of a silicon IP economy that fueled a productive design reuse strategy.

In the last decade, a more ominous productivity gap has emerged with respect to verification. While silicon complexity grows at the Moore’s Law rate, verification complexity grows at a significantly greater rate, and the approaches that were used to close the design productivity gap will be insufficient in closing the verification productivity gap. IBS quantified the impact of today’s verification gap in terms of IC project’s verification and validation cost with respect to decreasing process node feature size, as shown in the following graph.

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