HW/SW co-verification basics: Part 1 - Determining what & how to verify
Jason Andrews
5/23/2011 5:33 PM EDT
In this four part series, Jason Andrews details the importance of co-verification of both hardware and software in embedded system design and provides details on the various ways to achieve this. Part 1: Determining what and how to verify. The process of embedded system design generally starts with a set of requirements for what the product must do and ends with a working product that meets all of the requirements. Figure 6.1 below contains a list of the steps in the process and a short summary of what happens at each state of the design.
The requirements and product specification phase documents and defines the required features and functionality of the product. Marketing, sales, engineering, or any other individuals who are experts in the field and understand what customers need and will buy to solve a specific problem, can document product requirements.
Capturing the correct requirements gets the project off to a good start, minimizes the chances of future product modifications, and ensures there is a market for the product if it is designed and built. Good products solve real needs. have tangible benefits. and are easy to use.
To read the full article, click here
Related Semiconductor IP
- nQrux® Root of Trust IP
- AXI to UCIe Bridge IP
- UCIe 2.x Controller IP
- SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP
- OpenTitan-based RISC-V Secure Element
Related Articles
- Transaction-based methodology supports HW/SW co-verification
- Approaches to accelerated HW/SW co-verification
- HW/SW co-verification basics: Part 2 - Software-centric methods
- HW/SW co-verification basics: Part 3 - Hardware-centric methods
Latest Articles
- A Secure dToF LiDAR SoC with Dual-Domain Fingerprinting and Event-Driven AFE Circuit Achieving Sensor-Level Attack Resilience
- ZTA-Q: an Open-source RISC-V Platform for Accurate Quantized CNN Inference
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM