How SLEC improves functional verification
Leveraging System Models for RTL Functional Verification using Sequential Logic Equivalence Checking (SLEC).
By Anmol Mathur, Calypto Design Systems
edadesignline.com (January 23, 2009)
Design teams commonly use system models for verification. System models have many advantages over register transfer level (RTL) code for verification, notably, because of their ease of development and runtime performance. The ability to leverage the system-level verification to create functionally correct RTL code has challenged many a design team until now. A methodology known as Sequential Logic Equivalence Checking (SLEC) has the unique capability to formally verify RTL implementations against a specification written in C/C++ or System C.
This article will describe the system-level design flow of a commercial graphics processing chip. In this flow, system models have been developed to validate the arithmetic computation of video instructions and then used to verify the RTL implementation using the SLEC methodology.
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Articles
- Shifting from functional to structured techniques improves test quality
- How formal verification saves time in digital IP design
- Leveraging UVM based UFS Test Suite approach for Accelerated Functional Verification of JEDEC UFS IP
- SoC Functional verification flow
Latest Articles
- LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
- A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node
- Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework
- VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration
- CTTE: An Open Dual-Protocol RISC-V Trace Encoder for N-Trace and E-Trace