SoC Functional verification flow
Dilip Prajapati, eInfochips
December 14, 2017
This paper presents SoC- (System on Chip) level functional verification flow. It also describes ways to speed up the process.
To ensure successful tapeout of SoCs, here are the steps of a standard SoC-level Functional Verification flow:
1. SoC Level/Top Level view (Feature Extractions)
During SoC verification, you must view the design at the top level and extract its SoC level functionality/features during specification study phase for its verification. At this stage, a thorough understanding of SoC functionality and its architecture is required because misunderstanding of the specification can become the leading cause of bugs, and due to this you may waste unnecessary time on issues which are not real RTL problems.
2. SoC Level Verification Plan
- Define a Clear Line Between SoC and IP
During the development of the SoC level verification plan, you have to clearly define/identify the functionalities, which needs to be verified at the SoC level and at the sub-block or sub-IP or sub-cluster level. The same verification needs to be confirmed during the review with the respective verification team to avoid any last-minute surprises.
- Identify Reusability Components
You must also check which block or sub-block level verification components/environment and scenarios can be reused at the SoC level with a reusability point of view to reduce its new development time at SoC level.
- Verify Interconnections
At SoC level, you mainly have to focus on the top level functionalities of the SoC along with verifying whether the intercommunication between the sub-blocks occur properly or not. You have to also verify the connection of the sub-modules with the top. - Keep Placeholders for Updates
Sometimes, all the features of the SoC are not defined at the initial phase of the SoC verification planning. For those types of features, you need to update the verification plan at a later stage. Hence, during verification plan development, you can put placeholders or FIXME for the same to update the features when the need arises later on.
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Articles
- SoC Verification Flow and Methodologies
- Interconnect (NoC) verification in SoC design
- Shifting Mindsets: Static Verification Transforms SoC Design at RT Level
- Efficient methodology for verification of Dynamic Frequency Scaling of clocks in SoC
Latest Articles
- LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
- A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node
- Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework
- VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration
- CTTE: An Open Dual-Protocol RISC-V Trace Encoder for N-Trace and E-Trace