How much test compression is enough?
Chris Allsup, Synopsys
(02/20/2006 9:00 AM EST)
Each new manufacturing process generation brings with it a whole new set of challenges. In an era of multimillion-gate complexity and increasing density of nanometer manufacturing defects, a key challenge today is creating the highest quality deep submicron (DSM) manufacturing tests in the most cost-effective manner possible.
In an effort to contain costs at the tester, designers have begun to embrace a young, relatively obscure design for test (DFT) methodology known as scan compression that utilizes on-chip circuitry to compress the scan ATPG pattern set without otherwise compromising its fault coverage. Scan compression technology seems to have emerged at just the right time, offering designers the promise of reducing tester costs with only negligible impact on design performance, silicon overhead and engineering resources needed to implement compression on-chip.
(02/20/2006 9:00 AM EST)
Each new manufacturing process generation brings with it a whole new set of challenges. In an era of multimillion-gate complexity and increasing density of nanometer manufacturing defects, a key challenge today is creating the highest quality deep submicron (DSM) manufacturing tests in the most cost-effective manner possible.
In an effort to contain costs at the tester, designers have begun to embrace a young, relatively obscure design for test (DFT) methodology known as scan compression that utilizes on-chip circuitry to compress the scan ATPG pattern set without otherwise compromising its fault coverage. Scan compression technology seems to have emerged at just the right time, offering designers the promise of reducing tester costs with only negligible impact on design performance, silicon overhead and engineering resources needed to implement compression on-chip.
To read the full article, click here
Related Semiconductor IP
- nQrux® Root of Trust IP
- AXI to UCIe Bridge IP
- UCIe 2.x Controller IP
- SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP
- OpenTitan-based RISC-V Secure Element
Related Articles
- How Random is Random Enough For Cryptography?
- How to evaluate test compression methods
- EDA is not enough!
- How productive is your R&D organization?
Latest Articles
- A Secure dToF LiDAR SoC with Dual-Domain Fingerprinting and Event-Driven AFE Circuit Achieving Sensor-Level Attack Resilience
- ZTA-Q: an Open-source RISC-V Platform for Accurate Quantized CNN Inference
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM