EDA is not enough!
By Michel Tabusse
edadesignline.com (March 17, 2010)
Good EDA tools, even combined within well-automated flows, are not enough to produce quality designs, whatever those designs are for software, systems-on-chip (SoCs), integrated circuits (ICs), intellectual property (IP) or embedded systems. Why is quality so difficult to achieve? Here are some of the things we are finding:
- Quality is often not defined operationally, making measurement and reporting onerous.
- Tools may be used incorrectly.
- Quality reporting is often informal, not objective, or comprised of too much information to be actionable.
- Worldwide teams and concurrent IP/ SoC/ software design produce burdensome quality monitoring overhead.
- Quality compromises tend to be made in order to meet tight schedules.
How does one define quality measures so that they can be easily deployed and used? Every time there is a panel on quality, designers and design managers realize that a huge amount of question-and-answer time is spent on defining quality criteria. And that quality is not the same for every type of design or every company.
To read the full article, click here
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related Articles
- Colibri, the codec for perfect quality and fast distribution of professional AV over IP
- Agile Analog's Approach to Analog IP Design and Quality --- Why "Silicon Proven" is NOT What You Think
- IP users value quality, support
- SoCs: Supporting Socketization -> Methodology key to quality
Latest Articles
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs
- CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety